Patents by Inventor Utpal Bhattacharya

Utpal Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9746274
    Abstract: An apparatus for firing projectiles including a feeding mechanism adapted to feed projectiles into rotating arms rotating around an axis within a guide wall. The wall includes an opening through which the projectile are expelled due to the rotation of the arms. Strikers attached to each arm are so positioned so that they strike the projectile that has been expelled through the guide accelerating the projectile.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 29, 2017
    Inventor: Utpal Bhattacharya
  • Publication number: 20170241734
    Abstract: An apparatus for firing projectiles including a feeding mechanism adapted to feed projectiles into rotating arms rotating around an axis within a guide wall. The wall includes an opening through which the projectile are expelled due to the rotation of the arms. Strikers attached to each arm are so positioned so that they strike the projectile that has been expelled through the guide accelerating the projectile.
    Type: Application
    Filed: November 16, 2016
    Publication date: August 24, 2017
    Inventor: Utpal BHATTACHARYA
  • Patent number: 9202006
    Abstract: The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow for the assignment of a signal name to each stub. The method may include extending the stub for each of the selected pins to reach a target destination associated with the electronic design. The method may also include displaying the signal name for each stub on at least one of the first graphical user interface and the second graphical user interface.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli
  • Patent number: 8650518
    Abstract: A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: February 11, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Sanjay Gupta, Tarun Beri, Mohd Vaseem
  • Patent number: 8601422
    Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alok Tripathi, Abha Jain, Parag Choudhary, Utpal Bhattacharya
  • Patent number: 8527929
    Abstract: A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli, Tarun Beri, Rahul Verma
  • Patent number: 8479134
    Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli, Tarun Beri, Rahul Verma
  • Patent number: 8316337
    Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli, Tarun Beri, Rahul Verma
  • Publication number: 20110173582
    Abstract: A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal Bhattacharya, Sanjay Gupta, Tarun Beri, Mohd Vaseem
  • Publication number: 20110153289
    Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20110153288
    Abstract: A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20110154276
    Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Utpal BHATTACHARYA, Vikas KOHLI, Tarun BERI, Rahul VERMA
  • Publication number: 20100115487
    Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.
    Type: Application
    Filed: December 22, 2008
    Publication date: May 6, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Alok TRIPATHI, Abha JAIN, Parag CHOUDHARY, Utpal BHATTACHARYA