Patents by Inventor Uttam Shyamalindu Ghoshal

Uttam Shyamalindu Ghoshal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6430936
    Abstract: An apparatus for transporting and rejecting heat energy is provided. In one embodiment, the heat transporter includes a photonic microheatpipe and a source of photons. The photonic microheatpipe is a photonic crystal that shows pronounced Raman effect and is thermally coupled to a heat source. Photonic crystals disallow certain frequencies of light from being transmitted through the crystal. When a photon scatters back from phonons (lattice vibrations) in the crystal, the properties of the reflected spectrum are governed by the Raman effect. The reflected spectrum have two pronounced components: a Stoke's line and an Anti-Stokes line. The Stokes lines correspond to frequencies that are the difference between the frequency of the incident photons and that of the phonons, while the anti-Stokes lines correspond to frequencies that are sum of the frequency of the incident photons and that of the phonons.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6429694
    Abstract: An apparatus and method in an integrated circuit for detecting phase differences between clock signals originating from an oscillator circuit. The oscillator circuit is formed on a substrate, such that the oscillator circuit is coupled to coincidence elements responsive to clock signals originating from the oscillator circuit. In addition, a coincidence circuit is provided that includes the coincidence elements, such that the coincidence circuit provides output signals only in response to a change in all clock signals originating from the oscillator circuit. The apparatus includes a delay circuit responsive to the output signals, such that the delay circuit stretches delays between the clock signals. A phase detector is coupled to the delay circuit, such that the phase detector is responsible for detecting phase differences between the clock signals by identifying the delays.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6429137
    Abstract: A solid state thermal switch providing thermal conductivity in an ON state and enhanced thermal isolation in an OFF state. The thermal switch is manufactured on a substrate by forming an oxide layer under a thin semiconducting layer. The thin semiconducting layer can be made from silicon or a silicon geranium lattice structure. The thin silicon layer is cracked by a neutron bombardment process. A drain and a source are then doped into the thin silicon layer. Cracks in the thin silicon layer disrupt quiescent thermal conductivity in the electron transport layer between the drain and source when the solid state thermal switch is in the OFF state. The thin semiconducting layer transports electrons and heat when the solid state thermal switch is in the ON state. The cracks created in the silicon layer provide thermal isolation from the drain to the source when the thermal switch is in an OFF state and allow heat conduction when the solid state thermal device is in the ON state.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6429665
    Abstract: An impedance detection circuit includes a circuit input having a first contact and a second contact, a reference voltage rail coupled to the first contact, and a memory cell having a data node coupled to the second contact and an output. When the memory cell is read, the logic state of the output provides an indication of an impedance coupling the first and second contacts at the circuit input. The impedance detection circuit can be utilized to sense resistive and capacitive inputs and has any number of applications, including use as a digital hygrometer and as a fingerprint sensor.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Publication number: 20020092557
    Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes an electrical conductor thermally coupled to a cold plate and a thermoelement electrically coupled to the electrical conductor. The thermoelement is constructed from a thermoelectric material and has a plurality of tips through which the thermoelement is electrically coupled to the electrical conductor. The thermoelectric tips provide a low resistive connection while minimizing thermal conduction between the electrical conductor and the thermoelement.
    Type: Application
    Filed: December 7, 2000
    Publication date: July 18, 2002
    Applicant: IBM Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Publication number: 20020095243
    Abstract: A method and apparatus for characterization of a thermal response of giant magnetoresistive (GMR) sensors in magnetic read/write heads is provided. The method and apparatus make use of a probe to measure temperatures at a base and a tip of the probe. With the method and apparatus, a temperature of magnetic shields of the read/write head are cooled to a temperature lower than an ambient temperature. A current is then applied to the GMR sensor to increase a temperature of an air bearing surface such that the heat flow through the probe is zero. The amount of current applied, the resistance of the GMR sensor, the magnetic shield temperature, and the ambient temperature are used to calculate a thermal conductance of dielectric material in the read/write head. The thermal conductance is then utilized to estimate the signal to noise ratio of the GMR sensor and determine a maximum bandwidth of the read/write head.
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Inventor: Uttam Shyamalindu Ghoshal
  • Publication number: 20020092307
    Abstract: An apparatus for cooling selected elements within an integrated circuit, such as active transistors or passive circuit elements used in a radio frequency integrated circuit is provided. In one embodiment, the cooling apparatus includes a cold plate thermally coupled to the region proximate the integrated circuit element, a thermoelectric cooler thermally coupled to the cold plate; and a hot plate thermally coupled to the thermoelectric cooler. Heat is removed from the integrated circuit element through the cold plate and transmitted to the hot plate through the thermoelectric cooler. In one form, the hot plate is located or coupled to an exterior surface of an integrated circuit, such that heat transmitted to the ambient from the integrated circuit element is dissipated into the atmosphere surrounding the integrated circuit. In another form, the hot plate is embedded in the integrated circuit substrate to locally cool elements of the integrated circuit while dumping the heat into the substrate.
    Type: Application
    Filed: December 11, 2000
    Publication date: July 18, 2002
    Applicant: IBM Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Publication number: 20020071223
    Abstract: An improved read/write head for use in computer hard drives is provided. In one embodiment, the read/write head includes a first and second thermally conducting plates and a first and second stages of microcoolers. The second thermally conducting plate is thermally coupled to a read sensor of the read/write head. The second microcooler includes a hot plate and a cold plate, wherein the cold plate extends proximate the read sensor so as to cool the sensor to ambient or below temperatures. The first thermally conducting plate extends between the write coil and the read sensor in the read/write head and is thermally coupled to the hot plate of the second microcooler. The hot plate of the first microcooler is thermally coupled to one or more heat dissipation elements.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 13, 2002
    Applicant: IBM Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Publication number: 20020071222
    Abstract: A read/write head cooling system for use in a magnetic storage device, such as, for example, a hard disk drive is provided. In one embodiment, a thermally conducting patterned cold plate is thermally situated between a write coil and a read sensor of the read/write head. A microcooler, such as, for example, a thermoelectric cooler, is thermally coupled to the cold plate. A hot plate of one or more heat dissipation elements, such as, for example, copper posts, is thermally coupled to the hot side of the microcooler. The write coils of the read/write head are actively cooled by the microcooler to reduce the temperature of the write coil and read sensor in the head below that attainable with passive mechanisms.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 13, 2002
    Applicant: IBM Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6403876
    Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes a first thermoelement and a second thermoelement electrically coupled to the first thermoelement. An array of first tips are in close physical proximity to, but not necessarily in physical contact with, the first thermoelement at a first set of discrete points. An array of second tips are in close physical proximity to, but not necessarily in physical contact with, the second thermoelement at a second set of discrete points. The first and second conical are constructed entirely from metal, thus reducing parasitic resistances.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: June 11, 2002
    Assignee: International Business Machines Corporation
    Inventors: Uttam Shyamalindu Ghoshal, Errol Wayne Robinson
  • Publication number: 20020062648
    Abstract: An apparatus for dense chip packaging using heat pipes and thermoelectric coolers is provided. The apparatus includes an evaporator region, a condenser region, and a capillary region. The evaporator region includes one or more hot point elements used to transfer heat from a heat source to a transport fluid. The transport fluid changes state to a vapor when heat is applied to the transport fluid. The vapor travels to the condenser region via vapor channels and is condensed to a fluid once again by transferring heat from the vapor to a heat sink. The condensed fluid is then returned to the evaporator region by way of capillary forces and capillaries formed in a capillary structure. The capillaries formed in the capillary structure have a tree-like or fractal geometry. The apparatus may further include a flexible region that allows the apparatus to be bent around corners and edges.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6384312
    Abstract: A thermoelectric device with enhanced structured interfaces for improved cooling efficiency is provided. In one embodiment, the thermoelectric device includes a first thermoelement comprising a supetlattice of p-type thermoelectric material and a second thermoelement comprising superlattice of n-type thermoelectric material. The first and second thermoelements are electrically coupled to each other. The first thermoelement is proximate to, without necessarily being in physical contact with, a first array of electrically conducting tips at a discrete set of points. A planer surface of the second thermoelement is proximate to, without necessarily being in physical contact with, a second array of electrically conducting tips at a discrete set of points. The electrically conducting tips are coated with a material that has the same Seebeck coefficient as the material of the nearest layer of the superlattice to the tip.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventors: Uttam Shyamalindu Ghoshal, Steven A. Cordes, David Dimilia, James P. Doyle, James L. Speidell
  • Patent number: 6338251
    Abstract: Apparatus and method for sub-ambient cooling using thermoelectric cooling in convention with dynamics conventional cooling techniques. In one form, a vapor phase cooling system provides a temperature (T) and is associated with a thermoelectric cooler. The thermoelectric cooler provides a differential temperature &Dgr;T utilizing thermodynamics such as Peltier cooling. The thermoelectric cooler therefore provides a temperature of approximately T−&Dgr;T to an object.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: January 15, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6282907
    Abstract: Apparatus and method for sub-ambient cooling using thermoelectric dynamics in conjunction with novel configuration schemes to maximize energy transport to thereby increase the efficiency of thermoelectric cooling. In one form, a junction maximizes energy transport being positioned between and coupled to thermoelectric elements having minimal spacing to provide efficient thermoelectric cooling.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: September 4, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6266962
    Abstract: Apparatus, method, and signal for sub-ambient cooling using thermoelectric dynamics in conjunction with configurations and activation schemes to maximize the mean time between failure (MTBF) of thermoelectric coolers. In one form, a signal is provided which periodically alters the state of the Peltier devices from an active state to a passive state. During the active state the Peltier device provides maximum cooling and during the passive state the Peltier device minimizes thermal leakage while reducing cooling. Preferable implementations provide multiple signals to thermoelectric arrays such that, for a predetermined time, a first set of the arrays are in the active state while a second set of the arrays are in the passive state to thereby minimize failures and maximize the MTBF of the thermoelectric arrays.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6256996
    Abstract: Thermoelectric cooler for providing sub-ambient cooling and method of fabricating same. In one form, sub-micron thermoelectric coolers are formed using doped thin films as thermoelectric elements. The thin film thermoelectric elements are created on thermally and electrical isolating materials using an electrochemical deposition process with a junction formed between the thermoelectric elements. The sub-micron thermoelectric coolers can then be used to locally cool nanoscopic geometric regions such as regions of an integrated circuit or can be configured in an array for large scale microscopic cooling applications.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6221707
    Abstract: A method for fabricating a transistor having a variable threshold voltage is disclosed. Energy levels of a transistor can be represented by a valance band, a conduction band, and a Fermi level. In order to fabricate a transistor with a variable threshold voltage, a region of the transistor is initially doped with a first dopant having a first energy level below the Fermi level. The region of the transistor is subsequently doped with a second dopant having a second energy level above the Fermi level. Alternatively, the region of the transistor can be initially doped with a first dopant having a first energy level above the Fermi level, and then the region of the transistor can be subsequently doped with a second dopant having a second energy level below the Fermi level.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6222113
    Abstract: Thermoelectric cooler for providing sub-ambient cooling to an object and method of fabricating same. In one form, the thermally conducting but electrically insulating substrate interfaces used in conventional thermoelectric coolers are replaced by ultra-thin semiconductor substrates having a plurality of doped regions. Diodes formed in the semiconductor substrates are maintained in a reverse biased state to provide the desired electrical isolation necessary for operating the thermoelectric coolers. The reverse biased state is maintained by either the inherent properties resulting from forming the diode in the semiconductor material or through application of a bias voltage to the semiconductor substrates though a layer of conductive material deposited on the outermost surfaces of the substrates.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6208702
    Abstract: A system for synchronizing circuit operation within an integrated circuit having a high frequency clock is disclosed. The system includes an oscillator for providing a clock signal, and a clock signal complement. A two conductor transmission line is utilized to distribute the clock signal. The two conductor transmission line has a first conductor coupled to the clock signal and a second conductor coupled to the clock signal complement provides sub-circuits within the integrated circuit with a differential clock signal. Negative impedance transmission line terminations are then attached in parallel with the transmission line. The terminations boost the clock signal transition times and the clock signal complement transition times to provide high frequency circuit synchronization within the integrated circuit.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6204165
    Abstract: A method of fabricating an integrated circuit having air-gaps between interconnect levels. In a preferred embodiment, an integrated circuit is partially fabricated. The partially fabricated integrated circuit includes a top layer, interconnect structures having a cladding layer, dielectric layers and an etch stop layer resistant to certain first types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchants until the etch stop layer is reached. Thus, portions of the interconnect structures are exposed to create interconnect islands surrounded by air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal