Abstract: A charge measuring device detects focused ion beam attacks on an integrated semiconductor circuit with a capacitor, a field effect transistor, and a charge collecting device all manufactured in the integrated semiconductor circuit and insulated from additional circuit elements. A first pole of the capacitor is conductively connected to the charge collecting device and a gate of the field effect transistor. When a voltage is applied to the second pole of the capacitor, a drain source current flows through the field effect transistor, and a relationship between the voltage and the drain source current is ascertained. A comparison of the relationship with a previously ascertained relationship indicates a change of the charge quantity stored in the capacitor by the charge collecting device.

Abstract: A charge measuring device detects focused ion beam attacks on an integrated semiconductor circuit with a capacitor, a field effect transistor, and a charge collecting device all manufactured in the integrated semiconductor circuit and insulated from additional circuit elements. A first pole of the capacitor is conductively connected to the charge collecting device and a gate of the field effect transistor. When a voltage is applied to the second pole of the capacitor, a drain source current flows through the field effect transistor, and a relationship between the voltage and the drain source current is ascertained. A comparison of the relationship with a previously ascertained relationship indicates a change of the charge quantity stored in the capacitor by the charge collecting device.

Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

Abstract: Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.

Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Abstract: Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.

Abstract: A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch stop material is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges beneath the etch stop material.