Patents by Inventor Uwe Schmalzbauer
Uwe Schmalzbauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810958Abstract: A transistor includes: gate electrodes and field electrodes, wherein in each case one gate electrode and one field electrode are arranged one above another in a vertical direction in a common trench of a semiconductor body; a gate pad to which the gate electrodes are connected; and a source metallization arranged above the semiconductor body. The field electrodes of a first group include at least one contact section. The at least one contact section is arranged between two sections of a gate electrode arranged in the same trench and is connected to the source metallization. The two sections of the gate electrode are separated from one another in a region of the contact section. At least one of the two sections of the gate electrode arranged in the same trench is electrically connected to a gate electrode arranged in a further trench by way of a gate connecting electrode.Type: GrantFiled: August 12, 2021Date of Patent: November 7, 2023Assignee: Infineon Technologies AGInventors: Felix Buth, Margarete Deckers, Christian Feuerbaum, Uwe Schmalzbauer, Markus Zundel
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Patent number: 11804432Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.Type: GrantFiled: February 11, 2021Date of Patent: October 31, 2023Assignee: Infineon Technologies AGInventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
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Publication number: 20220254713Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
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Publication number: 20220052171Abstract: A transistor includes: gate electrodes and field electrodes, wherein in each case one gate electrode and one field electrode are arranged one above another in a vertical direction in a common trench of a semiconductor body; a gate pad to which the gate electrodes are connected; and a source metallization arranged above the semiconductor body. The field electrodes of a first group include at least one contact section. The at least one contact section is arranged between two sections of a gate electrode arranged in the same trench and is connected to the source metallization. The two sections of the gate electrode are separated from one another in a region of the contact section. At least one of the two sections of the gate electrode arranged in the same trench is electrically connected to a gate electrode arranged in a further trench by way of a gate connecting electrode.Type: ApplicationFiled: August 12, 2021Publication date: February 17, 2022Inventors: Felix Buth, Margarete Deckers, Christian Feuerbaum, Uwe Schmalzbauer, Markus Zundel
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Patent number: 9570433Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: GrantFiled: September 21, 2015Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Publication number: 20160254200Abstract: A semiconductor component includes a semiconductor body having a bottom side, a top side spaced distant from the bottom side in a vertical direction, and a thickness in the vertical direction, and a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body. A crack in the semiconductor body is detected by specifying a first value of a characteristic variable of the crack sensor, determining a second value of the characteristic variable of the crack sensor at a different time than the first value is specified, and determining the semiconductor body has a crack if the second value differs from the first value by more than a pre-defined difference.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Inventors: Markus Zundel, Uwe Schmalzbauer, Rudolf Zelsacher
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Patent number: 9343381Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.Type: GrantFiled: May 22, 2013Date of Patent: May 17, 2016Assignee: Infineon Technologies AGInventors: Markus Zundel, Uwe Schmalzbauer, Rudolf Zelsacher
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Publication number: 20160013176Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Patent number: 9218960Abstract: A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.Type: GrantFiled: June 30, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Peter Nelle, Uwe Schmalzbauer, Juergen Holzmueller, Markus Zundel
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Patent number: 9171777Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: GrantFiled: January 29, 2013Date of Patent: October 27, 2015Assignee: Infineon Technologies AGInventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Patent number: 8933448Abstract: Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.Type: GrantFiled: July 27, 2012Date of Patent: January 13, 2015Assignee: Infineon Technologies AGInventors: Markus Zundel, Uwe Schmalzbauer
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Publication number: 20140346509Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Inventors: Markus Zundel, Uwe Schmalzbauer, Rudolf Zelsacher
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Publication number: 20140315391Abstract: A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.Type: ApplicationFiled: June 30, 2014Publication date: October 23, 2014Inventors: Peter Nelle, Uwe Schmalzbauer, Juergen Holzmueller, Markus Zundel
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Patent number: 8803297Abstract: A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.Type: GrantFiled: August 10, 2012Date of Patent: August 12, 2014Assignee: Infineon Technologies AGInventors: Peter Nelle, Uwe Schmalzbauer, Juergen Holzmueller, Markus Zundel
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Publication number: 20140167044Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: ApplicationFiled: January 29, 2013Publication date: June 19, 2014Applicant: Infineon Technologies AGInventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Publication number: 20140167043Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Applicant: Infineon Technologies AGInventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Publication number: 20140042597Abstract: A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Nelle, Uwe Schmalzbauer, Juergen Holzmueller, Markus Zundel
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Publication number: 20140027772Abstract: Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: Infineon Technologies AGInventors: Markus ZUNDEL, Uwe SCHMALZBAUER
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Patent number: 8084865Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.Type: GrantFiled: April 30, 2008Date of Patent: December 27, 2011Assignee: Infineon Technologies AGInventors: Franz Hirler, Walter Rieger, Uwe Schmalzbauer, Rudolf Zelsacher, Markus Zundel
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Patent number: 7939885Abstract: A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.Type: GrantFiled: April 30, 2008Date of Patent: May 10, 2011Assignee: Infineon Technologies Austria AGInventors: Mathias Hans-Ulrich Alexander Von Borcke, Markus Zundel, Uwe Schmalzbauer