Patents by Inventor V. Krishnan
V. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230422639Abstract: A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Shafaat Ahmed, Gowtham Sriram Jawaharram, Cyrus M. Fox, Jose L. Cruz-Campa, Kriti Agarwal, Jian Jiao, Hong Li, Bharat V. Krishnan, Ervin T. Hill, III
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Publication number: 20230401185Abstract: A set of affinity metrics may be determined for a set of listings, each listing of the set of listings comprising data to be shared through a data exchange, wherein the set of affinity metrics includes a set of characteristics allowing identification of a listing having one or more characteristics in the set of characteristics. For each pair of listings of the set of listings, an affinity score can be calculated, using the set of affinity metrics, and stored as part of the record in an affinity store. One or more listings of the set of listings using the affinity score between the first listing of the set of listings and the one or more listings of the set of listings can be presented.Type: ApplicationFiled: February 22, 2023Publication date: December 14, 2023Inventors: Orestis Kostakis, Prasanna V. Krishnan, Subramanian Muralidhar, Shakhina Pulatova, Megan Marie Schoendorf
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Patent number: 11687506Abstract: Affinity-based listing recommendations are created and used in a public data exchange. Listings can be evaluated against one another for affinity or similarity such that users working with a particular dataset can be presented with other datasets that share an affinity. Affinity can be determined from both the dataset metadata as well as information from the dataset content. Calculation of affinity scores can be pre-computed and stored, in advance of use, or determined on-the-fly. Presentation of most-similar listings can be deterministic, can contain randomization, can employ time-decay, can be weighted, and can make use of a tiered-sum approach.Type: GrantFiled: July 25, 2022Date of Patent: June 27, 2023Assignee: Snowflake Inc.Inventors: Orestis Kostakis, Prasanna V. Krishnan, Subramanian Muralidhar, Shakhina Pulatova, Megan Marie Schoendorf
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Patent number: 11264382Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.Type: GrantFiled: July 30, 2020Date of Patent: March 1, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Jiehui Shu, Bharat V. Krishnan
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Patent number: 11094598Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.Type: GrantFiled: July 11, 2019Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Bharat V. Krishnan, Rinus Tek Po Lee, Jiehui Shu, Hyung Yoon Choi
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Publication number: 20210238523Abstract: The instant disclosure provides a system comprising a plurality of stacked bioreactors, wherein the system is configured to provide a substantially equal flow rate of fluid and pressure drop through each of the plurality of bioreactors. In some embodiments, the flow of the fluid through each of the plurality of bioreactors is configured to generate physiological shear rates to induce a biological source material in the bioreactors to produce target biological products.Type: ApplicationFiled: July 19, 2019Publication date: August 5, 2021Inventors: Jonathan N. Thon, Jorge Valdez, Marcus Lehmann, Douglas G. Sabin, Shawn Murphy, Shweta V. Krishnan
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Publication number: 20210013109Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Inventors: Bharat V. KRISHNAN, Rinus Tek Po LEE, Jiehui SHU, Hyung Yoon CHOI
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Publication number: 20210005601Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.Type: ApplicationFiled: July 30, 2020Publication date: January 7, 2021Applicant: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, Bharat V. Krishnan
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Patent number: 10811411Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.Type: GrantFiled: July 2, 2019Date of Patent: October 20, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, Bharat V. Krishnan
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Publication number: 20200312775Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: RINUS TEK PO LEE, FUAD AL-AMOODY, ASLI SIRMAN, JOSEPH KYALO KASSIM, HUI ZANG, BHARAT V. KRISHNAN
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Patent number: 10211045Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.Type: GrantFiled: January 24, 2018Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Jr., Rinus Tek Po Lee, Yiheng Xu
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Patent number: 10134876Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.Type: GrantFiled: March 31, 2017Date of Patent: November 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Bharat V. Krishnan, Timothy J. McArdle, Rinus Tek Po Lee, Shishir K. Ray, Akshey Sehgal
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Patent number: 10121706Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.Type: GrantFiled: November 28, 2016Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
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Publication number: 20180286982Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Bharat V. KRISHNAN, Timothy J. MCARDLE, Rinus Tek Po LEE, Shishir K. Ray, Akshey SEHGAL
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Publication number: 20180247936Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.Type: ApplicationFiled: February 27, 2017Publication date: August 30, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: SHISHIR K. RAY, BHARAT V. KRISHNAN, JINPING LIU, MEERA S. MOHAN, JOSEPH K. KASSIM
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Patent number: 10062692Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.Type: GrantFiled: February 27, 2017Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shishir K. Ray, Bharat V. Krishnan, Jinping Liu, Meera S. Mohan, Joseph K. Kassim
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Publication number: 20180151449Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
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Publication number: 20170068984Abstract: Offers are provided to consumers by a service on behalf of merchants in response to purchases by the consumer at the merchant, a collaborating merchant, or self-issued from a web site. Offers may be cloned by a consumer and provided to another user. Points may be assigned to consumers and used to purchase offers. Offers are generated with custom parameters for each customer. Offer parameters (e.g., duration, price, benefit) may be varied over time to determine successful parameters that are likely to result in offer redemption. Merchants may collaborate such that issuance of an offer for a first merchant results in issuance by the service of an offer for a second merchant. A fee may be charged by the service to the first merchant with at least a portion of the fee being paid to the second merchant.Type: ApplicationFiled: September 6, 2016Publication date: March 9, 2017Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
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Publication number: 20170033181Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Timothy J. McArdle, Judson R. Holt, Bharat V. Krishnan, Jody A. Fronheiser
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Publication number: 20160343016Abstract: Transaction parameters for a transaction between a customer and a merchant are provided to a reward service executing on a server system. The reward service assigns zero or more punches to the customer according to the transaction parameters based on legibility rules received from the merchant. The reward service further assigns a cash or points reward to the customer if punches assigned to the customer meet a threshold condition received by the reward service from the merchant. The reward may be assigned according to a tier of the customer, where the tier of the customer increases with a number of times the customer has met previously met the threshold condition. Punches may be provided to the customer as token including a token. The customer may then claim the token in order to associate the punch with the customer.Type: ApplicationFiled: May 18, 2016Publication date: November 24, 2016Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan