Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid may have slots of a particular aspect ratio which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The lower sub-chamber plasma has a lower electron density, lower effective electron temperature, and higher negative ion:positive ion ratio as compared to the upper sub-chamber plasma. The disclosed embodiments may result in an etching process having good center to edge uniformity, selectivity, profile angle, and Iso/Dense loading.

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.

Abstract: A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas; generating plasma from the first etch gas and second gas; and plasma etching an exposed surface of the semiconductor substrate.

Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract: A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The system includes a plasma processing chamber, a substrate support for supporting a substrate within the processing chamber, a dielectric member having an interior surface facing the substrate support, the dielectric member forming a wall of the processing chamber, a gas injector fixed to part of or removably mounted in an opening in the dielectric window, the gas injector including a plurality of gas outlets supplying process gas at adjustable flow rates to multiple zones of the chamber, and an RF energy source such as a planar or non-planar spiral coil which inductively couples RF energy through the dielectric member and into the chamber to energize the process gas into a plasma state.

Abstract: Components entirely of ceramic with etched surfaces wherein the etched surface has a surface roughness value or at least about 100 microinches (about 2.54 microns) Ra, and methods of forming such.

Abstract: In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.

Abstract: A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas; generating plasma from the first etch gas and second gas; and plasma etching an exposed surface of the semiconductor substrate.

Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a chamber. The chamber includes a gas inlet, a top electrode configured to strike a plasma inside the chamber, and a support for holding a substrate. A controller configured to detect a passivation starved condition during an etching operation is provided. The controller is further configured to introduce a passivation enhancing gas through the gas inlet during the etching operation in response to detecting the passivation starved condition.

Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract: A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.

Abstract: A method and apparatus for calibrating a semi-empirical process simulator used to determine process values in a plasma process for creating a desired surface profile on a process substrate includes providing a test model which captures all mechanisms responsible for profile evolution in terms of a set of unknown surface parameters. A set Sets of test conditions processes is are derived for which the profile evolution is governed by only a limited number of parameters. For each set of test conditions process, model test values are selected and a test substrate is substrates are actually subjected to a the test process processes defined by the test values , thereby creating a test surface profile profiles. The test values are used to generate an approximate profile prediction predictions and are adjusted to minimize the discrepancy between the test surface profile profiles and the approximate profile prediction predictions, thereby providing a final model of the profile evolution in terms of the process values.