Patents by Inventor Vajeed Nimran PARAMBIL ABDUL RAHEEM

Vajeed Nimran PARAMBIL ABDUL RAHEEM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Switched capacitor delay line
    Patent number: 11740208
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashuk Jain, Ravikumar Pattipaka, Vajeed Nimran Parambil Abdul Raheem, Sandeep Kesrimal Oswal
  • SWITCHED CAPACITOR DELAY LINE
    Publication number: 20210310996
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Prashuk JAIN, Ravikumar PATTIPAKA, Vajeed Nimran PARAMBIL ABDUL RAHEEM, Sandeep Kesrimal OSWAL
  • Switched capacitor delay line
    Patent number: 11067544
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashuk Jain, Ravikumar Pattipaka, Vajeed Nimran Parambil Abdul Raheem, Sandeep Kesrimal Oswal
  • SWITCHED CAPACITOR DELAY LINE
    Publication number: 20200129152
    Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 30, 2020
    Inventors: Prashuk JAIN, Ravikumar PATTIPAKA, Vajeed Nimran PARAMBIL ABDUL RAHEEM, Sandeep Kesrimal OSWAL