Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A lateral insulated gate transistor includes both a surface-adjoining drain region and a surface-adjoining anode region in an epitaxial surface layer. An anode-drain electrode is connected to the anode region and coupled to the drain region. In one embodiment of the device, the drain and anode regions are in direct contact, and the anode-drain electrode directly contacts both regions. In a second embodiment, the anode region is provided in a high-doped surface-adjoining region rather than in direct contact with the drain region, and the anode-drain electrode is coupled to the drain region through a resistive element. A third embodiment employs a Schottky contact connected to the anode-drain electrode. Lateral isolated gate rectifiers in accordance with the invention offer the advantages of low "on" resistance, high breakdown voltage and fast switching characteristics.