Patents by Inventor Valentin Abramzon
Valentin Abramzon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11711199Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: GrantFiled: December 16, 2021Date of Patent: July 25, 2023Assignee: Samsung Display Co., Ltd.Inventor: Valentin Abramzon
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Publication number: 20220109555Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: ApplicationFiled: December 16, 2021Publication date: April 7, 2022Inventor: Valentin Abramzon
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Patent number: 11206124Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: GrantFiled: December 1, 2020Date of Patent: December 21, 2021Assignee: Samsung Display Co., Ltd.Inventor: Valentin Abramzon
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Publication number: 20210083839Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: ApplicationFiled: December 1, 2020Publication date: March 18, 2021Inventor: Valentin Abramzon
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Patent number: 10862667Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: GrantFiled: March 12, 2020Date of Patent: December 8, 2020Assignee: Samsung Display Co., Ltd.Inventor: Valentin Abramzon
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Publication number: 20200213078Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Inventor: Valentin Abramzon
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Patent number: 10630461Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: GrantFiled: November 20, 2018Date of Patent: April 21, 2020Assignee: Samsung Display Co., Ltd.Inventor: Valentin Abramzon
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Publication number: 20200092077Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.Type: ApplicationFiled: November 20, 2018Publication date: March 19, 2020Inventor: Valentin Abramzon
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Patent number: 10444785Abstract: A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.Type: GrantFiled: August 22, 2018Date of Patent: October 15, 2019Assignee: Samsung Display Co., Ltd.Inventor: Valentin Abramzon
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Publication number: 20190286186Abstract: A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.Type: ApplicationFiled: August 22, 2018Publication date: September 19, 2019Inventor: Valentin Abramzon
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Publication number: 20190286178Abstract: A comparator. The comparator includes two back-to-back inverters, a differential pair, and a first common mode compensation transistor. The differential pair has two outputs configured to receive respective series currents from, or supply respective series currents to, the back-to-back inverters. The first common mode compensation transistor is configured to supply a compensating current to, or draw a compensating current from, a first output of the two outputs of the differential pair.Type: ApplicationFiled: August 7, 2018Publication date: September 19, 2019Inventors: Da Wei, Valentin Abramzon
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Publication number: 20190280591Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.Type: ApplicationFiled: August 22, 2018Publication date: September 12, 2019Inventors: Valentin Abramzon, Amir Amirkhany, Anup P. Jose
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Patent number: 10411593Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.Type: GrantFiled: August 22, 2018Date of Patent: September 10, 2019Assignee: Samsung Display Co., Ltd.Inventors: Valentin Abramzon, Amir Amirkhany, Anup P. Jose
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Patent number: 10401391Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.Type: GrantFiled: August 3, 2018Date of Patent: September 3, 2019Assignee: Samsung Display Co., Ltd.Inventors: Da Wei, Mohammad Hekmat, Valentin Abramzon, Amir Amirkhany
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Publication number: 20190265278Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.Type: ApplicationFiled: August 3, 2018Publication date: August 29, 2019Inventors: Da Wei, Mohammad Hekmat, Valentin Abramzon, Amir Amirkhany
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Patent number: 9397677Abstract: A system and method: provide a digital input signal to a digital-to-analog converter (DAC) which, in response to a DAC clock signal, converts the digital input signal to an analog output signal; generate from the DAC clock signal a sampling clock signal having pulses spaced apart from each other in time by a plurality of DAC clock periods, wherein a timing of at least one of the pulses is offset with respect to the DAC clock signal by a first fraction of a DAC clock period, and a timing of at least an other one of the pulses of the sampling clock signal is offset with respect to the DAC clock signal by a second fraction of the DAC clock period; sample-and-hold the analog output signal in response to the sampling clock signal; and digitize the sampled-and-held analog output signal to output digital values representing the sampled-and-held analog output signal.Type: GrantFiled: November 2, 2015Date of Patent: July 19, 2016Assignee: Keysight Technologies, Inc.Inventor: Valentin Abramzon
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Patent number: 9166574Abstract: An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment.Type: GrantFiled: December 17, 2010Date of Patent: October 20, 2015Assignee: Keysight Technologies, Inc.Inventor: Valentin Abramzon
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Patent number: 8885671Abstract: A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.Type: GrantFiled: September 10, 2010Date of Patent: November 11, 2014Assignee: Keysight Technologies, Inc.Inventors: Gunter Steinbach, Valentin Abramzon
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Patent number: 8842033Abstract: A predistortion generator includes a sample input, a summing circuit to output predistorted samples to a DAC, and distortion term processors, each including a product generator and a FIR filter in tandem. The distortion term processors include a second-order and/or a third-order distortion term processor. In the second-order distortion term processor, the product generator generates a product of only two samples corresponding to a current sample as a respective second-order distortion term that is filtered by the FIR filter thereof using a respective FIR filter characteristic. In the third-order distortion term processor, the product generator generates a product of only three samples corresponding to the current sample as a respective third-order distortion term that is filtered by the FIR filter thereof using a respective FIR filter characteristic. The FIR filter characteristics of FIR filters are configured to reduce distortion in a designated Nyquist zone.Type: GrantFiled: September 30, 2013Date of Patent: September 23, 2014Assignee: Agilent Technologies, Inc.Inventor: Valentin Abramzon
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Publication number: 20130335130Abstract: An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment.Type: ApplicationFiled: December 17, 2010Publication date: December 19, 2013Applicant: Agilent Technologies, IncInventor: Valentin Abramzon