Abstract: A phase error integrator for determining the phase error between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one embodiment the phase error integrator is formed as two functional components, namely a phase error detector and an integrator chain. The phase error detector sends to the integrator one of two output signals depending on whether the phase error is positive or negative. The integrator chain has a number of outputs the first half of which initially have a binary 1 and the second half of which initially have a binary 0. Depending on which output signal arrives from the phase error detector the binary 1's shift right or the binary 0's shift left. The integrator may be combined with a delay block connected to the outputs of the integrator chain. The data signal is fed to the delay block and delayed data output signal is obtained which is connected to the data input of the phase error integrator.

Abstract: A double-star communications system comprises a digital terminal, active pedestals coupled to the digital terminal via optical fibers, and subscribers' premises coupled to each active pedestal via existing telephone lines and via additional communications paths, which may comprise optical fibers or coaxial calbes. The digital terminal multiplexes broadband signal components, such as video channels, selected in response to subscriber control signals, with a multiplexed telephony signal and transmits these optically to an active pedestal, and receives the control signals, a multiplexed telephony signal, and optional upstream broadband signal components from the active pedestal. The active pedestal transmits and receives the signals on the first communications path, and demultiplexes the received multiplexed telephony signal and the broadband signal components.