Abstract: An SRT division unit for performing a novel SRT division algorithm is presented. The novel SRT division algorithm comprises a method for performing SRT division using a radix r. As one skilled in the art will appreciate, the radix r dictates the number of quotient-bits k generated during a single iteration. The relationship between radix r and the number of quotient-bits k generated in a single iteration is r=2k. The number of iterations needed to determine all quotient-digits is N, such that N=54/k for a 64 bit floating point value. In accordance with one embodiment of the present invention, the SRT division unit generates a scaling factor M, which comprises scaling sub-factors M1 and M2 according to the relationship M=r*M1+M2. Next, the division unit generates a scaled divisor Y by multiplying a divisor DR by scaling factor M, such that said scaled divisor Y=DR*M=r(DR*M1)+DR*M2.

Abstract: In a wide instruction architecture processor device, an instruction execution unit provides integer and floating point capability within its constituent arithmetic logic channels. Results are written out to a register file where integer results are given higher priority over floating point results, which are buffered, in order to increase integer operation throughput. By buffering floating point results and giving priority to integer results, fewer register file write ports are needed. A bypass mechanism allows access to floating point results during their pendency in the buffer. Dual serially-configured integer units are configured to enable two-operand and combined (three-operand) instructions to be delivered to an arithmetic and logic channel at every clock cycle. Similarly, dual parallel pipelined floating point units are configured to permit two-operand and combined (three-operand) floating point instructions to be delivered to an arithmetic and logic channel on each clock cycle.

Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.

Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.

Abstract: Floating point performance in a VLIW processor is increased through concatenation of two floating point units, one an adder and another a multiplier, which execute independently of one another but which operate in cooperation for certain combinations of issued operations. In particular, the floating point adder and the floating point multiplier may be activated individually by very long instruction words, which are also called wide instructions, that issue operations to either unit or both units at one time. For other wide instructions, both the floating point adder and the floating point multiplier may be sequentially activated by a single instruction with three operands. The first two operands are used by one of the units, either the floating point adder or the floating point multiplier, and the unit is activated.

Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles occur with no instructions started, subsequent fast instructions are executed by the fast execution path.

Abstract: A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit") does not. The result of the rounding subunit is selected as the addition result when one of the following conditions (R1), (R2), (R3) is true: (R1) the operation is an effective addition; (R2) the operation is an effective subtraction, the magnitude ED of the difference between the exponents of the operands is 1, and normalization of the result is not required; (R3) the operation is an effective subtraction and ED>1. The addition result is selected from the non-rounding subunit in the remaining cases. In some embodiments, the rounding subunit overlaps rounding with adding the operands, significands. In some embodiments, the addition unit satisfies ANSI/IEEE Standard 754-1985.

Abstract: A central processor for scientific-technica, economic-statistical computations, for solving the problems of modelling and control with the architecture of an extended instruction work comprises instruction data buffer memories 1 and 3, respectively, a control device 2, a data commutator 4, an arithmeticologic device 5, record-calling, indexing, associative memory, mathematical-to-physical address conversion, interface, subprogram device (6-11), as well as a control character device 13 and an operand readiness device 14, and provides high efficiency both on vector and scalar computations.