Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: A glass core substrate for an integrated circuit (IC) device may be formed to include a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract: Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes.

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.

Abstract: Embodiments of the invention include a piezoelectric package integrated filtering device that includes a film stack. In one example, the film stack includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The film stack is suspended with respect to a cavity of an organic substrate having organic material and the film stack generates an acoustic wave to be propagated across the film stack in response to an application of an electrical signal between the first and second electrodes.

Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.