Patents by Inventor Vamsee Vardhan Chivukula
Vamsee Vardhan Chivukula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230101654Abstract: Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load to a destination, wherein the destination may be either the texture sampler or the data port; wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing availability of the data port.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Carlos Nava Rodriguez, Yoav Harel, Joydeep Ray, Abhishek R. Appu, Vamsee Vardhan Chivukula, Benjamin R. Pletcher
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Patent number: 11615584Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: GrantFiled: July 22, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Publication number: 20220383569Abstract: Methods, systems and apparatuses may provide for technology that selects a location of a pixel block based on a location of a graphics polygon, wherein the pixel block contains the graphics polygon. The technology may also convert the graphics polygon into a pixel-based representation within the pixel block during a single transaction.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Jorge Garcia Pabon, Subramaniam Maiyuran, Raghavendra Kamath Miyar, Vamsee Vardhan Chivukula, Krishan Malik, Abhishek Varshney
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Patent number: 11494867Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.Type: GrantFiled: December 8, 2020Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Saurabh Sharma, Michael Apodaca, Aditya Navale, Travis Schluessler, Vamsee Vardhan Chivukula, Abhishek Venkatesh, Subramaniam Maiyuran
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Publication number: 20220051473Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: ApplicationFiled: July 22, 2021Publication date: February 17, 2022Applicant: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Patent number: 11250539Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: GrantFiled: July 16, 2020Date of Patent: February 15, 2022Assignee: INTEL CORPORATIONInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Publication number: 20210256653Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.Type: ApplicationFiled: December 8, 2020Publication date: August 19, 2021Applicant: Intel CorporationInventors: Saurabh Sharma, Michael Apodaca, Aditya Navale, Travis Schluessler, Vamsee Vardhan Chivukula, Abhishek Venkatesh, Subramaniam Maiyuran
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Patent number: 11080925Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: GrantFiled: June 28, 2019Date of Patent: August 3, 2021Assignee: INTEL CORPORATIONInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Publication number: 20210035259Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: ApplicationFiled: July 16, 2020Publication date: February 4, 2021Applicant: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Publication number: 20200402196Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.Type: ApplicationFiled: June 21, 2019Publication date: December 24, 2020Applicant: Intel CorporationInventors: Saurabh Sharma, Michael Apodaca, Aditya Navale, Travis Schluessler, Vamsee Vardhan Chivukula, Abhishek Venkatesh, Subramaniam Maiyuran
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Patent number: 10861126Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.Type: GrantFiled: June 21, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Saurabh Sharma, Michael Apodaca, Aditya Navale, Travis Schluessler, Vamsee Vardhan Chivukula, Abhishek Venkatesh, Subramaniam Maiyuran
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Patent number: 10748242Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: GrantFiled: July 26, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Publication number: 20200098167Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: ApplicationFiled: June 28, 2019Publication date: March 26, 2020Applicant: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Patent number: 10424107Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: GrantFiled: April 1, 2017Date of Patent: September 24, 2019Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Patent number: 10319138Abstract: An embodiment of graphics apparatus may include a coarse depth tester to perform a coarse depth test on a block of pixels, and a stencil tester to perform a stencil test on the block of pixels. The stencil tester may be further configured to perform the stencil test in parallel with the coarse depth test. Other embodiments are disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Prasoonkumar Surti, Abhishek R. Appu, Andrew S. Downsworth, Vamsee Vardhan Chivukula, Akshay Chada, Karol A. Szerszen, Joydeep Ray, Bryon T. Rogers
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Publication number: 20190038222Abstract: In some embodiments, the disclosed subject matter is an assistance system with a wearable assistive device that mitigates the effects of neuro-muscular ailments such as unintended motion, or loss of strength. The assistance system uses predictive analysis based on situational, operational, and historical contexts, when in active/predictive mode. When in reactive triode, the assistive device mitigates unintended motion without altering the strength of the user. The assistance system may have an exercise mode to both assess the user's strength and flexibility of various muscles and joints, and promote exercises to either avoid further losses, or to maintain current strength and flexibility. The assistance system utilizes sensor data from sensors coupled to the assistive device, and optionally from sensors coupled to mobile devices and in the environment. Actuators on the assistive device control movement of the device based on inferred intended actions or reactive to unintended movement.Type: ApplicationFiled: May 23, 2018Publication date: February 7, 2019Inventors: Yuri Krimon, Shirisha Middela, Katalin Bartfai-Walcott, Ingrid Murphy, Vamsee Vardhan Chivukula, Michael Imhoff, Olugbemisola Oniyinde
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Publication number: 20190026855Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: ApplicationFiled: July 26, 2018Publication date: January 24, 2019Applicant: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Patent number: 10102609Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: GrantFiled: April 1, 2017Date of Patent: October 16, 2018Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Publication number: 20180286011Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
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Publication number: 20180286102Abstract: An embodiment of graphics apparatus may include a coarse depth tester to perform a coarse depth test on a block of pixels, and a stencil tester to perform a stencil test on the block of pixels. The stencil tester may be further configured to perform the stencil test in parallel with the coarse depth test. Other embodiments are disclosed and claimed.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Inventors: Vasanth Ranganathan, Saikat Mandal, Prasoonkumar Surti, Abhishek R. Appu, Andrew S. Downsworth, Vamsee Vardhan Chivukula, Akshay Chada, Karol A. Szerszen, Joydeep Ray, Bryon T. Rogers