Abstract: Techniques efficiently improve circuit design to reduce its sensitivity to random device variation. A characterizer component can identify a subset of cells for an integrated circuit that can be representative of respective other cells of a set of cells. The characterizer component can analyze the representative cells of the subset to generate a variation profile, and can map the representative cells to physical cells used in the design of the circuit. A cell library comprising cells that are usable, have limited usage, and/or have general usage can be generated based on analysis results from the mapped cells. The circuit can be reconstructed based on the list of available cells using the cell library. The reconstructed circuit can be analyzed, and in case of a cell(s) violating a constraint, the cell(s) can be modified or enhanced to achieve target performance criteria.

Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

Abstract: Aspects of the disclosure embody methods and circuits for delaying a trigger signal. In one embodiment, a trigger delay circuit receives a trigger-in signal, delays some predetermined and programmable time delay and then outputs a trigger-out signal. The trigger delay circuit, in one embodiment, includes a programmable trigger circuit that time stamps the input trigger signal, delay for a predetermined time, and output the output trigger signal after the predetermined time.

Abstract: Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.

Abstract: Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.

Abstract: Imaging Parallel Interface Random Access Memory (IPIRAM). An integrated circuit imaging device presents to external circuitry as a static, parallel-interface RAM. Internally, a two-port RAM has access resolved by contention logic to permit access by external circuitry or internal imaging. The RAM is organized as one or more image buffers and a set of memory-mapped control and status registers. The imaging array, when active, automatically fills an image buffer with image data, which may be accessed by external circuitry in random-access fashion. Control and status registers may be used to start and stop the imaging process, set and interrogate imaging parameters. The IPIRAM may also include auxiliary processing circuitry to perform functions such as image compression, scaling, edge and feature extraction, and the like.

Abstract: Imaging serial interface ROM (ISIROM). An integrated circuit imaging device presents to external circuitry as a read-only memory (ROM) with a serial interface. The ISIROM contains internal memory which stores data from the imaging array. When active, the imaging array automatically fills an image buffer in the internal memory with image data. This image data may be accessed by external circuitry in random-access fashion. Control and status registers may be used to start and stop the imaging process, set and interrogate imaging parameters. The ISIROM may also include auxiliary processing circuitry to perform functions such as image compression, scaling, edge and feature extraction, and the like.

Abstract: A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.

Abstract: An upconverting circuit is disclosed. The upconverting circuit includes a polyphase component generator that provides Np polyphase components at each input polyphase cycle, wherein Np>2 on each input polyphase cycle defined by a clock. A memory stores the polyphase components from at least one polyphase cycle prior to the current polyphase cycle. A plurality of filters process the polyphase components stored in the memory. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexer outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory is a shift register. The filters can be of arbitrary complexity.

Abstract: A flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states. The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states.