Patents by Inventor Van Huynh

Van Huynh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7043708
    Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: May 9, 2006
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Duc Van Huynh
  • Publication number: 20060009842
    Abstract: Improved, adaptable tissue-type heart valves and methods for their manufacture are disclosed wherein a dimensionally stable, pre-aligned tissue leaflet subassembly is formed and its peripheral edge clamped between and attached to an upper shaped wireform and a lower support stent. A variety of adaptable structural interfaces including suture rings, flanges, and conduits may be attached to the support stent with or without an outlet conduit disposed about the wireform to provide a tissue-type heart valve adaptable for use in either a natural heart or in mechanical pumping devices. The methods include forming individual leaflets with a template and using the template to attach the leaflets together to form a tissue leaflet subassembly. The template and leaflets include a straight edge terminating in oppositely directed tabs, and a curvilinear cusp edge extending opposite the straight edge.
    Type: Application
    Filed: August 12, 2005
    Publication date: January 12, 2006
    Inventors: Van Huynh, Than Nguyen, Hung Lam, Xiaoming Guo, Ralph Kafesjian
  • Publication number: 20050243638
    Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.
    Type: Application
    Filed: July 1, 2005
    Publication date: November 3, 2005
    Inventors: Matthew Harrington, Van Huynh, Adin Hyslop
  • Publication number: 20040250225
    Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.
    Type: Application
    Filed: June 9, 2003
    Publication date: December 9, 2004
    Inventors: Alexander Tetelbaum, Duc Van Huynh
  • Patent number: 6810505
    Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: October 26, 2004
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Maad A. Al-Dabagh, Duc Van Huynh, Ruben Molina, Jr.
  • Publication number: 20040010761
    Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: Alexander Tetelbaum, Maad A. Al-Dabagh, Duc Van Huynh, Ruben Molina
  • Publication number: 20020076402
    Abstract: The invention concerns a fungicidal or fungistatic composition comprising, in combination, at least one glycolytic enzyme and its substrate and/or oligomers thereof; a process for preparing said compositions; and their use.
    Type: Application
    Filed: April 26, 2001
    Publication date: June 20, 2002
    Applicant: Universite Pierre et Marie Curie
    Inventors: Chadi Khouri, Michel Minier, Francois Le Goffic, Nguyen Van Huynh
  • Patent number: 6209170
    Abstract: A resilient door knob bumper receives a door knob in an aperture, the deformation of the resilient bumper retaining the door knob in position in the aperture.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: April 3, 2001
    Inventor: Son Van Huynh
  • Patent number: 6004766
    Abstract: A method is provided for the detection of low levels of a microorganism in a sample in the presence of competing microflora, comprising the steps of: (a) exposing the sample to a solid support to which are adsorbed antibodies specific for said microorganism; (b) washing the solid support to remove unbound material; (c) combining the solid support with sterile nutrient broth which permits replication of said microorganism; (d) incubating the solid support with said nutrient broth at a temperature and for a time sufficient to allow said microorganism to replicate and be recaptured by said antibodies on said solid support; (e) releasing the bound microorganism from the solid support into a solution; and (f)assaying the solution for the microorganism. A kit for performing the assay also is provided.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: December 21, 1999
    Assignee: Biotechnology Australia Pty Limited
    Inventors: Vincent H. Atrache, Megan Ash, Ca Van Huynh
  • Patent number: 5415997
    Abstract: The invention relates to methods for the detection of low numbers of a particular microorganism or microorganisms from a mixed population, the method comprising exposing the sample to a solid support to which antibodies specific for the organism(s) are adsorbed and either growing the bound organism(s) to a detectable level followed by immunoassay or releasing the organisms from the support followed by growth on a non-selective medium and observation of the resultant colonies. The invention also relates to test kits for performing these methods.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: May 16, 1995
    Assignee: Biotechnology Australia PTY Limited
    Inventors: Vincent H. Atrache, Megan Ash, Ca Van Huynh