Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

Abstract: A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes executing a first test pattern from a plurality of test patterns of a logic built-in self test (LBIST). The method further includes generating a first value based on the first test pattern. The method also further includes comparing the first value to a second value, and terminating the LBIST in response to determining that the first value does not equal the second value.

Abstract: A software program to translate a Verilog UDP (User Defined Primitive) into basic logic gates, in order to allow easier porting into other HDL languages and non-Verilog models, such as the LogicVision model. In a preferred embodiment the program is in Perl script, and reads in a Verilog source file. On finding a UDP, the script writes out a gate level description of the UDP into a Perl hash data structure, which is later used to output a LogicVision model.