Patents by Inventor Vanessa PENA

Vanessa PENA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326925
    Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Andrew Anthony Cockburn, Vanessa Pena, Daniel Philippe Cellier, John Tolle, Thomas Kirschenheiter, Wei Hong, Ellie Y. Yieh, Mehul Naik, Seshadri Ramaswami
  • Patent number: 11145761
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Publication number: 20200035822
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Patent number: 10490666
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Nam Sung Kim, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood
  • Patent number: 10177227
    Abstract: The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 8, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Naomi Yoshida, Lin Dong, Shiyu Sun, Myungsun Kim, Nam Sung Kim, Dimitri Kioussis, Mikhail Korolik, Gaetano Santoro, Vanessa Pena
  • Publication number: 20180061978
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi Sun WOOD, Nam Sung KIM
  • Patent number: 9865735
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Publication number: 20160336405
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM