Patents by Inventor Vasanth Bala

Vasanth Bala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010049818
    Abstract: A method for operating a code cache in a dynamic instruction translator, comprising the steps of: storing a plurality of translations in a cold partition in a cache memory; maintaining a different associated counter for each of a plurality of translations in the cold partition of the cache memory; incrementing or decrementing the count in the associated counter each time its associated translation is executed; and moving the translation to a hot partition in the cache memory if the count in the associated counter reaches a first threshold value.
    Type: Application
    Filed: January 5, 2001
    Publication date: December 6, 2001
    Inventors: Sanjeev Banerjia, Evelyn Duesterwald, Vasanth Bala
  • Publication number: 20010042172
    Abstract: A method for growing a secondary trace out of a cache of translations for a program during the program's execution in a dynamic translator, comprising the steps of: maintaining execution counts for translation heads that are executed from a code cache; when an execution count for one of said translation heads exceeds a threshold, designated as a hot translation head, beginning a mode of operation in which, as following code translations are executed from the code cache after the execution of the hot translation head, storing in a history buffer information identifying each of the following code translations in sequence; terminating the storing of information in the history buffer in relation to the hot translation head when a termination condition is met; and linking together the translation head and the sequence of following code translations identified in the history buffer to form a larger code translation.
    Type: Application
    Filed: January 5, 2001
    Publication date: November 15, 2001
    Inventors: Evelyn Duesterwald, Vasanth Bala, Sanjeev Banerjia
  • Publication number: 20010042173
    Abstract: In a system and method for linking and unlinking code fragments stored in a code cache, a memory area is associated with a branch in a first code fragment that branches outside the cache. If the branch can be set to branch to a location in a second code fragment stored in the cache, branch reconstruction information is stored in the memory area associated with the branch, and the branch instruction is updated to branch to the location in the second code fragment, thereby linking the first code fragment to the second code fragment. If it is determined that the previously linked branch should be unlinked, the first and second code fragments at that branch are unlinked by reading the information stored in the associated memory area at the time of linking, and using that information to reset the branch to its state prior to the linking.
    Type: Application
    Filed: January 5, 2001
    Publication date: November 15, 2001
    Inventors: Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia
  • Publication number: 20010032306
    Abstract: An optimization scheme used at run-time or compile-time is capable of identifying partially redundant loads and determining whether the load is truly redundant. The truly redundant load may be replaced with a register copy instruction to reduce the memory traffic and save CPU cycle time.
    Type: Application
    Filed: January 5, 2001
    Publication date: October 18, 2001
    Inventors: Evelyn Duesterwald, Vasanth Bala, Sanjeev Banerjia
  • Patent number: 6237065
    Abstract: Cache apparatus and method with a cache replacement strategy that preemptively evicts native code translations from a code cache, independent of a space shortage in the code cache. Replacement timing is based on detection by the dynamic translator of a change in a parameter that is indicative of either two things: 1) a change in the working set of the program being translated (a parameter such as a translation rate) or 2) a change in the paths being exercised within the current working set of the program being translated (a parameter such as or the accuracy of branch predictions). This apparatus and method is described in the context of a dynamic translator.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: May 22, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Sanjeev Banerjia, Vasanth Bala, Evelyn Duesterwald
  • Patent number: 6233678
    Abstract: An apparatus and method are shown for collecting a branch history value of a program executing in a processor. A current start address register latches a program count value in response to a trace termination condition, such as an indirect branch instruction. A current branch history register is cleared in response to the trace termination condition and shifts in a branch outcome value of the processor in response to a conditional direct branch instruction. A last trace start address latches the content of the current trace start address and a last branch history register latches the content of the current branch history register when a trace termination condition occurs.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: May 15, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Vasanth Bala