Abstract: The present disclosure disclose method and apparatus for determining memory requirement for processing a DNN model on a device, a method includes receiving a DNN model for an input, wherein the DNN model includes a plurality of processing layers. The method includes generating a network graph of the DNN model. The method includes creating a colored network graph of the DNN model based on the identified execution order of the plurality of processing layers. The colored network graph indicates assignment of at least one memory buffer for storing at least one output of at least one processing layer. The method includes determining at least one buffer reuse overlap possibility across the plurality of processing layers. Based on the determined at least one buffer reuse overlap possibility, the method includes determining and assigning the memory required for processing the DNN model.

Abstract: Systems, apparatuses, and methods for implementing one-sided per-kernel clipping and weight transformation for neural networks are disclosed. Various parameters of a neural network are quantized from higher-bit representations to lower-bit representations to reduce memory utilization and power consumption. To exploit the effective range of quantized representations, positively biased weights are clipped and negated before convolution. Then, the results are rescaled back after convolution. A one-sided clipping technique is used for transforming weights to exploit the quantization range effectively, with the side chosen to be clipped being the biased side. This technique uses a global strategy for clipping without requiring skilled expertise. This approach allows the system to retain as much information as possible without losing unnecessary accuracy when quantizing parameters from higher-bit representations to lower-bit representations.

Abstract: The present disclosure disclose method and apparatus for determining memory requirement for processing a DNN model on a device, a method includes receiving a DNN model for an input, wherein the DNN model includes a plurality of processing layers. The method includes generating a network graph of the DNN model. The method includes creating a colored network graph of the DNN model based on the identified execution order of the plurality of processing layers. The colored network graph indicates assignment of at least one memory buffer for storing at least one output of at least one processing layer. The method includes determining at least one buffer reuse overlap possibility across the plurality of processing layers. Based on the determined at least one buffer reuse overlap possibility, the method includes determining and assigning the memory required for processing the DNN model.

Abstract: A method and system for accelerating collision resolution of 3D physics engine on a reconfigurable processor allows the collision resolution module to utilize the immense parallelism available in Coarse Grained Array (CGA) of reconfigurable processor based on ADRES. The method of rescheduling and dividing the collision pairs is performed for accelerating the collision resolution. The method obtains the colliding pairs in the original order of processing from the objects that are under simulation. Then the method starts reordering the collision pairs for removing the dependency between the successive collision pairs. The independent collision pairs obtained from the original colliding pairs are grouped together. The dependent collision pairs are extracted and grouped together. The independent collision pairs are processed in CGA mode by utilizing the loop level parallelism, whereas the dependent collision pairs are processed in VLIW mode.

Abstract: A method and system for accelerating collision resolution of 3D physics engine on a reconfigurable processor allows the collision resolution module to utilize the immense parallelism available in Coarse Grained Array (CGA) of reconfigurable processor based on ADRES. The method of rescheduling and dividing the collision pairs is performed for accelerating the collision resolution. The method obtains the colliding pairs in the original order of processing from the objects that are under simulation. Then the method starts reordering the collision pairs for removing the dependency between the successive collision pairs. The independent collision pairs obtained from the original colliding pairs are grouped together. The dependent collision pairs are extracted and grouped together. The independent collision pairs are processed in CGA mode by utilizing the loop level parallelism, whereas the dependent collision pairs are processed in VLIW mode.