Abstract: A shielded inductor in an integrated circuit includes conductive loops disposed on a deep-well noise shield for isolating a noise coupling between the conductive loops and the substrate of the integrated circuit. The deep-well noise shield includes a first well disposed within a second well that is disposed within the substrate of the integrated circuit. The second well includes a peripheral well, a deep-well layer, and slot wells. The peripheral well surrounds a periphery of the first well. The peripheral well and the deep-well layer are coupled together to provide two p-n junctions that separate the first well and the substrate. The slot wells are distributed inside the periphery of the first well. Each slot well and the deep-well layer are coupled together. Each slot well has a width and a length that is at least three times the width.

Abstract: A receiver frontend includes a first input junction for receiving a first input signal, a second input junction for receiving a second input signal, a first output junction, a second output junction, and circuitry configured to perform equalization on the first input signal and the second input signal to establish a first output signal with a desired frequency response at the first output junction, and to establish a second output signal with a desired frequency response at the second output junction, and perform common-mode voltage adjustment on a common-mode voltage associated with the first output signal and the second output signal.

Abstract: A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electro-static discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second terminal of the inductor circuit. A method of generating an output signal is also disclosed.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass gate.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

Abstract: An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.

Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.

Abstract: An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor die and a heat spreader of the integrated circuit device for conducting heat from the semiconductor die to the heat spreader. The thermal interface material includes diamond particles and has a thickness selected to reduce capacitance between the semiconductor die and the heat spreader over that of a conventional integrated circuit device without reducing the rate of thermal conduction from the semiconductor die to the heat spreader. As a result, the integrated circuit device has improved electrostatic discharge immunity.

Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.

Abstract: A symmetrical inductor includes pairs of half-loops, first and second terminal electrodes, and a center-tap electrode. The half-loop pairs are in respective conductive layers of an integrated circuit. Each half-loop pair includes a first and second half-loop in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.

Abstract: The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils.

Abstract: The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils.

Abstract: A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.

Abstract: An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected to a node between the source of the NMOS transistor and the output of the pass gate. A current clamp is connected between the node and a current sink so as to conduct current to the current sink when the node reaches a threshold value.

Abstract: A device for generating a tensile force between a substrate and a coating, wherein the substrate has a thickness defined by a first side and a second side in a first axis, and the coating is applied to the first side of the substrate such that the coating and substrate are axially spaced along the first axis in intimate facing contact with each other to form a coating/substrate interface. The apparatus has a glass element disposed on the second side of the substrate and axially spaced along the first axis. The glass element is configured to propagate a stress wave to the coating/substrate interface to generate a tensile force between the substrate and the coating.