Patents by Inventor Vassilios C. Gerousis

Vassilios C. Gerousis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10192018
    Abstract: An improved approach is described to implement trim data representation for an electronic design. Instead of maintaining a gap shape object for every gap in the layout, existing objects adjacent to the gap location are configured to include attributes of the gap shape. The properties of the gap shape can then be derived from the adjacent objects.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vassilios C. Gerousis, Shane Zhang, Jianmin Li, Stefanus Mantik, Louis Tsai
  • Patent number: 9767245
    Abstract: Methods and systems for enhancing electronic designs for improving mask designs and manufacturability of electronic circuit designs for multi-exposure lithography are disclosed. The methods identify gap rectangles in a design and create gap blocks with the some of the identified gap rectangles according to at least their positions in a design and design rules. A relation graph is determined among the gap blocks or gap rectangles. The methods adjust some gap blocks by altering their sizes or dimensions. Some gap blocks may be split into multiple smaller gap blocks. The methods convert some gap rectangles into metal fill(s) and/or metal extensions to generate a structured physical design based at least in part upon the gap blocks and/or the multiple smaller gap blocks.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 19, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stefanus Mantik, Vassilios C. Gerousis