Patents by Inventor Vasudev J. Bibikar

Vasudev J. Bibikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Securing external memory data
    Patent number: 9235712
    Abstract: The present disclosure includes apparatus, systems, digital logic circuitry and techniques relating to data encoding. A method performed by a system on a chip (SOC) includes receiving data to be output to a memory unit external to the SOC. Also a key for scrambling the received data is received. A proper subset of the key is identified and used to scramble the received data. The scrambled data is output to the memory unit external to the SOC.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: January 12, 2016
    Assignee: Marvell International Ltd.
    Inventors: Vasudev J. Bibikar, Minda Zhang, David Hawkins, Paul A. Lambert
  • Securing external memory data
    Patent number: 8555082
    Abstract: The present disclosure includes apparatus, systems, digital logic circuitry and techniques relating to data encoding. A method performed by a system on a chip (SOC) includes receiving data to be output to a memory unit external to the SOC. Also a key for scrambling the received data is received. A proper subset of the key is identified and used to scramble the received data. The scrambled data is output to the memory unit external to the SOC.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 8, 2013
    Assignee: Marvell International Ltd.
    Inventors: Vasudev J. Bibikar, Minda Zhang, David Hawkins, Paul A. Lambert
  • Method and apparatus for waking up a circuit
    Patent number: 7770044
    Abstract: An indication that a power supply is ramped up to a threshold level is received. A circuit is woken up in response to receiving the indication if a control field of configuration information is in a first state, and the circuit is not woken up in response to receiving the indication if the control field of configuration information is in a second state.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: August 3, 2010
    Assignee: Marvell International Ltd.
    Inventors: Vasudev J. Bibikar, Mark N. Fullterton, James R. Feddeler
  • Power fault handling method, apparatus, and system
    Patent number: 7334158
    Abstract: A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Vasudev J. Bibikar, Mark N. Fullerton
  • Power supply detection method, apparatus, and system
    Patent number: 7302600
    Abstract: Circuits in a processor may provide an indication that power supplies are ready when waking from a reduced power state. The processor may include timers to measure a period of time, and may utilize voltage detectors to detect the voltages on the power supplies. A control register in the processor may influence the operation.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 27, 2007
    Assignee: Marvell International Ltd.
    Inventors: Vasudev J. Bibikar, Mark N. Fullterton, James R. Feddeler
  • Apparatus and method for optimizing performance of a cache memory in a data processing system
    Patent number: 6192449
    Abstract: A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15). If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: February 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Joseph C. Circello, Anup S. Tirumala, Vasudev J. Bibikar
  • Cache memory in a data processing system
    Patent number: 5765190
    Abstract: A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15) If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: June 9, 1998
    Assignee: Motorola Inc.
    Inventors: Joseph C. Circello, Anup S. Tirumala, Vasudev J. Bibikar