Abstract: A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.

Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Abstract: Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

Abstract: Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

Abstract: Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

Abstract: Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

Abstract: An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls enabling the clock distribution to the CKDOMs according to the scheduled sequence.

Abstract: A threshold voltage generation circuit includes a control transistor, one or more load transistors, and a current mirror. The load transistors are diode-connected transistors that are operated in saturation. The source-to-gate voltage of the load transistors approximates the threshold voltage of the transistors over process and temperature. The operation of the circuit is affected by choosing a bias voltage for the control transistor, the sizes of the control transistor and load transistors, and the ratio of transistor sizes within the current mirror.

Abstract: A threshold voltage generation circuit includes a control transistor, one or more load transistors, and a current mirror. The load transistors are diode-connected transistors that are operated in saturation. The source-to-gate voltage of the load transistors approximates the threshold voltage of the transistors over process and temperature. The operation of the circuit is affected by choosing a bias voltage for the control transistor, the sizes of the control transistor and load transistors, and the ratio of transistor sizes within the current mirror.

Abstract: A current reference has two control transistors sized and biased to generate two control currents. The two control currents change over process variations such that the difference between the two currents remains substantially constant over process variations. A current mirror receives and mirrors the difference current to provide a substantially process-independent output current.