Patents by Inventor Veera M. Gunturu

Veera M. Gunturu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9443782
    Abstract: A method for protecting terminal elements on a wafer during wafer level fabrication processes entails applying a protective coating to the terminal elements prior to further processing operations. These processing operations may include back side grinding of the wafer and/or saw-to-reveal operations to expose the terminal elements from a cap wafer of a wafer structure. The protective coating can protect the terminal elements from potentially damaging contaminants, such as debris from the grinding or saw-to-reveal operations. Furthermore, the protective coating can protect the bond pads from coming into contact with a rapidly oxidizing environment when exposed to water. The protective coating may be a hot-water soluble thermoplastic material the melts from a solid form to a liquid form at a relatively low temperature to enable application of the protective coating in liquid form onto the terminal elements and clean removal of the protective coating from the terminal elements.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 13, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Dwight L. Daniels, Veera M. Gunturu
  • Patent number: 8039312
    Abstract: A capped micro-electro-mechanical systems (MEMS) device is formed using a device wafer and a cap wafer. The MEMS device is located on a frontside of the device wafer. A frontside of a cap wafer is attached to the frontside of the device wafer. A first stressor layer having a tensile stress is applied to a backside of the cap wafer after attaching the frontside of the cap wafer to the frontside of the device wafer. The first stressor layer and the cap wafer are patterned to form an opening through the first stressor layer and the cap wafer after applying the first stressor layer. A conductive layer is applied to the backside of the cap wafer, including through the opening to the frontside of the device wafer.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: October 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Veera M. Gunturu, Shivcharan V. Kamaraju, Lisa H. Karlin