Abstract: A physical (PHY) circuit can include a Physical Medium Dependent (PMD) circuit, the PMD circuit having a receiver and a transmitter, a Physical Medium Attachment (PMA) circuit coupled to the PMD circuit, and a plurality of Physical Coding Sublayer (PCS) circuits coupled to the PMA circuit, wherein each PCS circuit is configured to implement a different communication protocol. The PHY circuit can also include an auto-negotiation circuit coupled to the PMD circuit, wherein the auto-negotiation circuit is configured to determine a selected communication protocol compatible with a link partner device from a plurality of communication protocols by configuring the receiver to operate at different data rates over time, the different data rates corresponding to different ones of the plurality of communication protocols.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.