Patents by Inventor Veeresh Deshpande

Veeresh Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11988904
    Abstract: The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si1-xGex pseudosubstrate layer with 0<x?1 and with a third refractive index. The center layer is grown on the Si1-xGex pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field (Ev) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: May 21, 2024
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / LEIBNIZ-INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
    Inventors: Andreas Mai, Patrick Steglich, Christian Mai, Catherine Dubourdieu, Veeresh Deshpande, Dong-Jik Kim
  • Publication number: 20220197066
    Abstract: The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si1-xGex pseudosubstrate layer with 0<x?1 and with a third refractive index. The center layer is grown on the Si1-xGex pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field (E) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 23, 2022
    Applicant: Helmholtz-Zentrum Berlin für Materialien und Energie GmbH
    Inventors: Andreas MAI, Patrick STEGLICH, Christian MAI, Catherine DUBOURDIEU, Veeresh DESHPANDE, Dong-Jik KIM
  • Patent number: 10256092
    Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
  • Publication number: 20170294307
    Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 12, 2017
    Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
  • Patent number: 9704757
    Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine