Patents by Inventor Veeresh Vidyadhar Deshpande
Veeresh Vidyadhar Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11205716Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.Type: GrantFiled: October 24, 2019Date of Patent: December 21, 2021Assignee: IMEC VZWInventors: Veeresh Vidyadhar Deshpande, Bertrand Parvais
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Patent number: 11138501Abstract: A method for hardware-implemented training of a feedforward artificial neural network is provided. The method comprises: generating a first output signal by processing an input signal with the network, wherein a cost quantity assumes a first cost value; measuring the first cost value; defining a group of at least one synaptic weight of the network for variation; varying each weight of the group by a predefined weight difference; after the variation, generating a second output signal from the input signal to measure a second cost value; comparing the first and second cost values; and determining, based on the comparison, a desired weight change for each weight of the group such that the cost function does not increase if the respective desired weight changes are added to the weights of the group. The desired weight change is based on the weight difference times ?1, 0, or +1.Type: GrantFiled: February 22, 2018Date of Patent: October 5, 2021Assignee: International Business Machines CorporationInventors: Stefan Abel, Veeresh Vidyadhar Deshpande, Jean Fompeyrine, Abu Sebastian
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Patent number: 10957854Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer is arranged between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.Type: GrantFiled: September 27, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
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Publication number: 20200203509Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.Type: ApplicationFiled: October 24, 2019Publication date: June 25, 2020Inventors: Veeresh Vidyadhar Deshpande, Bertrand Parvais
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Publication number: 20200028079Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer is arranged between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Inventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
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Patent number: 10516108Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.Type: GrantFiled: February 27, 2019Date of Patent: December 24, 2019Assignee: International Business Machines CorporationInventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
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Publication number: 20190312199Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.Type: ApplicationFiled: February 27, 2019Publication date: October 10, 2019Inventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
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Patent number: 10395732Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.Type: GrantFiled: May 4, 2018Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
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Publication number: 20190258926Abstract: The invention relates to a method for hardware-implemented training of a feedforward artificial neural network. The method comprises: generating a first output signal by processing an input signal with the network, wherein a cost quantity to assumes a first cost value; measuring the first cost value; defining a group of at least one synaptic weight of the network for variation; varying each weight of the group by a predefined weight difference; after the variation, generating a second output signal from the input signal to measure a second cost value; comparing the first and second cost values; and determining, based on the comparison, a desired weight change for each weight of the group such that the cost function does not increase if the respective desired weight changes are added to the weights of the group. The desired weight change is based on the weight difference times ?1, 0, or +1.Type: ApplicationFiled: February 22, 2018Publication date: August 22, 2019Inventors: Stefan Abel, Veeresh Vidyadhar Deshpande, Jean Fompeyrine, Abu Sebastian
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Patent number: 10312441Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.Type: GrantFiled: April 9, 2018Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
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Publication number: 20180254083Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
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Patent number: 10037800Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.Type: GrantFiled: September 28, 2016Date of Patent: July 31, 2018Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
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Publication number: 20180090203Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudanan Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
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Patent number: 9881921Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: GrantFiled: April 10, 2017Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9786664Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: GrantFiled: February 10, 2016Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170229352Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: April 10, 2017Publication date: August 10, 2017Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170229460Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1?x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: February 10, 2016Publication date: August 10, 2017Inventors: Lukas CZORNOMAZ, Veeresh Vidyadhar DESHPANDE, Vladimir DJARA, Jean FOMPEYRINE
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Patent number: 9673104Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.Type: GrantFiled: February 10, 2016Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9564452Abstract: A method is disclosed for fabricating a semiconductor circuit. A semiconductor substrate is provided. A first semiconductor device is fabricated including a first semiconductor material on the substrate and forming an insulating layer including a cavity structure on the first semiconductor device. The cavity structure includes at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure including a second semiconductor material different from the first semiconductor material in the growth channel, forming a semiconductor starting structure for a second semiconductor device from the filling structure, and fabricating a second semiconductor device including the starting structure. Corresponding semiconductor circuits are also disclosed.Type: GrantFiled: February 1, 2016Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine