Patents by Inventor Veit Gernhoefer

Veit Gernhoefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8448124
    Abstract: A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Uwe Fassnacht, Veit Gernhoefer, Michael S. Gray, Joachim Keinert
  • Publication number: 20130074025
    Abstract: A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: International Business Machines Corporation
    Inventors: Uwe Fassnacht, Veit Gernhoefer, Michael S. Gray, Joachim Keinert
  • Patent number: 7865848
    Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veit Gernhoefer, Michael S. Gray, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker, Bruce C. Wheeler
  • Patent number: 7568173
    Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
  • Publication number: 20090112963
    Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wilhelm Haller, Guenter Mayer, Veit Gernhoefer, Ulrich Krauch, Simon Fabel
  • Publication number: 20090064061
    Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventors: Veit Gernhoefer, Michael S. Gray, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker, Bruce C. Wheeler
  • Publication number: 20080313581
    Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
  • Publication number: 20080071852
    Abstract: A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wilhelm Haller, Guenter Mayer, Veit Gernhoefer, Ulrich Krauch, Simon Fabel
  • Patent number: 7315994
    Abstract: In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: January 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ingo Aller, Veit Gernhoefer, Joachim Keinert, Thomas Ludwig
  • Publication number: 20050136582
    Abstract: In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Ingo Aller, Veit Gernhoefer, Joachim Keinert, Thomas Ludwig