Patents by Inventor Vencent Chang
Vencent Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080206679Abstract: Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Vencent Chang, Norman Chen, Kuei Shun Chen, Chin-Hsiang Lin
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Publication number: 20080204688Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
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Publication number: 20080153012Abstract: A method of measuring the overlay accuracy of a multi-exposure process is provided. The characteristic of this invention is utilizing a scanning electron microscope for monitoring the overlay accuracy real-time during the multi-exposure processes in stead of the conventional optical measurement method.Type: ApplicationFiled: February 13, 2008Publication date: June 26, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: George Liu, Vencent Chang, Chia-Chen Chen
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Patent number: 7387969Abstract: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.Type: GrantFiled: March 18, 2005Date of Patent: June 17, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: George Liu, Vencent Chang, Norman Chen, Yao-Ching Ku, Chin-Hsiang Lin, Kuei Shun Chen
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Publication number: 20080128924Abstract: A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Vencent Chang, Chin-Hsiang Lin, Kuei Shun Chen, Norman Chen
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Publication number: 20080102648Abstract: A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer whereupon the portion of the buffer layer and the portion of the resist layer are removed to form a process window substantially free of resist residue that can be subsequently exploited for etching of the semiconductor device layer.Type: ApplicationFiled: November 1, 2006Publication date: May 1, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Hsiao-Tzu Lu, Kuei Shun Chen, Ching-Yu Chang, Vencent Chang
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Publication number: 20070224795Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).Type: ApplicationFiled: July 12, 2006Publication date: September 27, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun CHEN, Chin-Hsiang LIN, Vencent CHANG, Lawrence LIN, Lai Chien WEN, Jhun Hua CHEN
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Publication number: 20060211254Abstract: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.Type: ApplicationFiled: March 18, 2005Publication date: September 21, 2006Inventors: George Liu, Vencent Chang, Norman Chen, Yao-Ching Ku, Chin-Hsiang Lin, Kuei Chen
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Publication number: 20050244729Abstract: A method of measuring the overlay accuracy of a multi-exposure process is provided. The characteristic of this invention is utilizing a scanning electron microscope for monitoring the overlay accuracy real-time during the multi-exposure processes in stead of the conventional optical measurement method.Type: ApplicationFiled: April 29, 2004Publication date: November 3, 2005Applicant: United Microelectronics Corp.Inventors: George Liu, Vencent Chang, Chia-Chen Chen
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Publication number: 20050123863Abstract: An immersion lithography process is described as follows. A photoresist layer and a protective layer are sequentially formed on a material layer, and then an immersion exposure step is performed to define an exposed portion and an unexposed portion in the photoresist layer. A solubilization step is conducted to solubilize the protective layer on the exposed portion of the photoresist layer, and then a development step is conducted to remove the exposed portion of the photoresist layer and the protective layer thereon. Since the photoresist layer is covered with the protective layer, the chemicals in the photoresist layer do not diffuse into the immersion liquid to cause contamination. The protective layer can be patterned simultaneously in the development step, and no extra step is required to remove the protective layer. Therefore, the whole lithography process is not complicated.Type: ApplicationFiled: December 3, 2003Publication date: June 9, 2005Inventors: Vencent Chang, George Liu, Norman Chen
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Patent number: 6844143Abstract: A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.Type: GrantFiled: August 2, 2002Date of Patent: January 18, 2005Assignee: United Microelectronics Corp.Inventors: Benjamin Szu-Min Lin, Vencent Chang, George Liu, Cheng-Chung Chen
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Publication number: 20040166447Abstract: First of all, a semiconductor substrate with a photoresist layer thereon is provided. Then a plurality of pattern photoresists with a first line width are formed on the semiconductor substrate by a photolithography process. Next, an acid-process is performed to form a diffusion layer having the acid-based materials on the plurality of pattern photoresists and the semiconductor substrate. Afterward, a re-baking process is performed to diffuse the acid-based materials within diffusion layer into the plurality of pattern photoresists such that the acid-based materials chain-react with the plurality of pattern photoresist located on the diffusion depth of the acid-based materials so as to form a plurality of reaction layers within the skin layers of the plurality of pattern photoresists, wherein the diffusion depth of the acid-based materials in the plurality of pattern photoresists depends on the diffuse rate of the acid-based materials in the acid-process.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Inventors: Vencent Chang, Chia-Chen Chen, George Liu, Benjamin Szu-Min Lin, Cheng-Chung Chen
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Publication number: 20040166448Abstract: First of all, a semiconductor substrate with a photoresist layer thereon is provided. Then a photoresist region is formed on the semiconductor substrate by a photolithography process. Next, a chemical reaction layer is formed within the photoresist region. Subsequently, a developing process is performed to remove the chemical reaction layer within the photoresist region to shrink the photoresist region in line width on the semiconductor substrate.Type: ApplicationFiled: November 21, 2003Publication date: August 26, 2004Applicant: United Microelectronics Corp.Inventors: Vencent Chang, George Liu, Chia-Chen Chen, Benjamin Szu-Min Lin, Cheng-Chung Chen
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Patent number: 6680252Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming a dual damascene interconnect structure, by use of the present invention, a planar topography of the BARC layer is achieved by chemical mechanical polishing. The present invention applies a low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of the BARC layer is provided before coating the photoresist, so formation of the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on the via and the critical dimension control for the via are improved by patterning the via on a planar and an anti-reflective surface.Type: GrantFiled: May 15, 2001Date of Patent: January 20, 2004Assignee: United Microelectronics Corp.Inventors: Anseime Chen, Hui-Ling Huang, Vencent Chang, Andersen Chang
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Publication number: 20040009434Abstract: A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.Type: ApplicationFiled: August 2, 2002Publication date: January 15, 2004Applicant: UNITED MICROELECTRONICS CORP.Inventors: Benjamin Szu-Min Lin, Vencent Chang, George Liu, Cheng-Chung Chen
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Publication number: 20020173152Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming dual damascene interconnect structure, by use of the present invention, a planar topography of BARC layer is achieved by chemical mechanical polishing. The present invention applies low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of BARC layer is provided before coating the photoresist, so the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on via and the critical dimension control for via are improved by patterning via on a planar and anti-reflective surface.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Inventors: Anseime Chen, Hui-Ling Huang, Vencent Chang, Andersen Chang
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Patent number: 6458705Abstract: In accordance with the present invention, a method for forming a via-first dual damascene interconnect structure by using gap-filling material whose thickness is easily controlled by a developer is provided. The essential part of the present invention is the application of gap-filling materials such as novolak, PHS, acrylate, methacrylate, and COMA to fill vias. Filling vias with these materials can get a greater planar topography for trench patterning due to its excellent gap-filling capacity, protect the bottom of vias from damage during the trench etch, and prevent the fence problem by using a developer to control its thickness in vias.Type: GrantFiled: June 6, 2001Date of Patent: October 1, 2002Assignee: United Microelectronics Corp.Inventors: Kuei-Chun Hung, Vencent Chang, I-Hsiung Huang, Ya-Hui Chang