Abstract: An e-learning system has a local classroom with an instructor station and a microphone and a local student station with a microphone, a remote classroom with an instructor display and a student station with a microphone, and planar displays and video cameras in each of the classrooms, the remote and local classrooms connected over a network, with a server monitoring feeds and enforcing exclusive states, such that audio and video feeds are managed in a manner that video and audio of the instructor, the local students and the first remote students, as seen and heard either directly or via speakers and displays by each of the instructor, the local students and the remote students presents to each as though all are interacting in the same room.

Abstract: Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not.

Abstract: Methods and apparatus are provided for determining synapses in an artificial nervous system based on connectivity patterns. One example method generally includes determining, for an artificial neuron, an event has occurred; based on the event, determining one or more synapses with other artificial neurons based on a connectivity pattern associated with the artificial neuron; and applying a spike from the artificial neuron to the other artificial neurons based on the determined synapses. In this manner, the connectivity patterns (or parameters for determining such patterns) for particular neuron types, rather than the connectivity itself, may be stored. Using the stored information, synapses may be computed on the fly, thereby reducing memory consumption and increasing memory bandwidth. This also saves time during artificial nervous system updates.

Abstract: An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.

Abstract: An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.

Abstract: Techniques describe computing computer vision (CV) features based on sensor readings from a sensor and detecting macro-features based on the CV features. The sensor may include a sensor element array that includes a plurality of sensor elements. The sensor may also include in-pixel circuitry coupled to the sensor elements, peripheral circuitry and/or a dedicated microprocessor coupled to the sensor element array. The in-pixel circuitry, the peripheral circuitry or the dedicated microprocessor may include computation structures configured to perform analog or digital operations representative of a multi-pixel computation for a sensor element (or block of sensor elements), based on sensor readings generated by neighboring sensor elements in proximity to the sensor element, and to generate CV features. The dedicated microprocessor may process the CV features and detect macro-features.

Abstract: An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.

Abstract: Techniques disclosed herein utilize a vision sensor that integrates a special-purpose camera with dedicated computer vision (CV) computation hardware and a dedicated low-power microprocessor for the purposes of detecting, tracking, recognizing, and/or analyzing subjects, objects, and scenes in the view of the camera. The vision sensor processes the information retrieved from the camera using the included low-power microprocessor and sends “events” (or indications that one or more reference occurrences have occurred, and, possibly, associated data) for the main processor only when needed or as defined and configured by the application. This allows the general-purpose microprocessor (which is typically relatively high-speed and high-power to support a variety of applications) to stay in a low-power (e.g., sleep mode) most of the time as conventional, while becoming active only when events are received from the vision sensor.

Abstract: A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling.

Abstract: A method for computing a spatial Fourier transform for an event-based system includes receiving an asynchronous event output stream including one or more events from a sensor. The method further includes computing a discrete Fourier transform (DFT) matrix based on dimensions of the sensor. The method also includes computing an output based on the DFT matrix and applying the output to an event processor.

Abstract: A method of interfacing an event based processing system with a frame based processing system is presented. The method includes converting multiple events into a frame. The events may be generated from an event sensor. The method also includes inputting the frame into the frame based processing system.

Abstract: A set of trigrams can be generated for each document in a plurality of documents processed by an e-discovery system. Each trigram in the set of trigrams for a given document is a sequence of three terms in the given document. A set of trigrams for each similar document is then determined based on the set of trigrams for the original document. To facilitate identification of the similar documents, a full text index is then generated for the plurality of documents and the set of trigrams for each document are indexed into the full text index, as individual terms. Queries can be generated into the full text index based on trigrams of a document to determine other similar or near-duplicate documents. After a set of potentially similar documents are identified, a separate distance criteria can be applied to evaluate the level of similarity between the two documents in an efficient way.

Abstract: An apparatus reducing power theft on a micro power grid includes a server connected to the micro power grid, the server including a processor, data repository and software executing on the processor from a non-transitory medium the software enabling collection over time of bi-directional current data from smart distribution nodes connected to identified segments of the micro power grid and from smart meters distributed to one or more client demarcation points on the identified segments, processing of the bi-directional current data to determine power theft event frequency and power theft current information, assigning of a class to the individual ones of identified segments according to results of processing, and resetting of the number of packet transmission hop counts between the smart distribution nodes on identified segments and resetting the time period interval between subsequent power theft check routines for each identified segment based upon the classification data.

Abstract: Certain aspects of the present disclosure support a technique for adaptive bit-allocation in neural systems. Bit-allocation for neural signals and parameters in a neural network described in the present disclosure may comprise for a plurality of synapse circuits in the neural simulator network, dynamically allocating a number of bits to the neural circuit signals based on at least one characteristic of one or more neural potential in the neural simulator network; and for the plurality of synapse circuits in the neural simulator network, dynamically allocating a number of bits to at least one neural processing parameter of the synapse circuit based on at least one condition of the neural simulator network.

Abstract: Apparatus and methods for partial evaluation of synaptic updates in neural networks. In one embodiment, a pre-synaptic unit is connected to a several post synaptic units via communication channels. Information related to a plurality of post-synaptic pulses generated by the post-synaptic units is stored by the network in response to a system event. Synaptic channel updates are performed by the network using the time intervals between a pre-synaptic pulse, which is being generated prior to the system event, and at least a portion of the plurality of the post synaptic pulses. The system event enables removal of the information related to the portion of the post-synaptic pulses from the storage device. A shared memory block within the storage device is used to store data related to post-synaptic pulses generated by different post-synaptic nodes. This configuration enables memory use optimization of post-synaptic units with different firing rates.

Abstract: Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.

Abstract: A server computing system determines a plurality of statistics for a plurality of validation documents. The server computing system determines a plurality of statistics for a plurality of test documents. The number of test documents in the plurality of test documents is determined based on the plurality of statistics for the plurality of validation documents and the effectiveness measure of interest. The server computing system calculates an effectiveness of an information retrieval system on a corpus of documents based on the plurality of statistics for the plurality of test documents.

Abstract: A method for transmitting values in a neural network includes obtaining a parameter value. The method also includes encoding the parameter value based on at least one value used by a neuron. The encoding is based on a spike to be transmitted via a spike channel.

Abstract: An exemplary predictive coding system can be programmed to update a plurality of training documents based on a portion of a training document selected by a user. The predictive coding system generates a machine learning engine based on the updated plurality of training documents. The predictive coding system predicts a classification for one or more remaining documents from the plurality of training documents using the machine learning engine.

Abstract: Aspects of the present disclosure relate to methods and apparatus for training an artificial nervous system. According to certain aspects, timing of spikes of an artificial neuron during a training iteration are recorded, the spikes of the artificial neuron are replayed according to the recorded timing, during a subsequent training iteration, and parameters associated with the artificial neuron are updated based, at least in part, on the subsequent training iteration.