Abstract: A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Abstract: Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface.

Abstract: Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.

Abstract: Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface.

Abstract: A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Abstract: A memory system may include an optimized data compaction algorithm. The compaction may include transferring only valid data from a source block to a destination block. A compaction bitmap that is maintained in random access memory (“RAM”) may be populated during the compaction process. The populated bitmap may be used to copy valid fragments to the destination block.

Abstract: A memory system may include an optimized data compaction algorithm. The compaction may include transferring only valid data from a source block to a destination block. A compaction bitmap that is maintained in random access memory (“RAM”) may be populated during the compaction process. The populated bitmap may be used to copy valid fragments to the destination block.