Patents by Inventor Venkata Narayanan Srinivasan
Venkata Narayanan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983025Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.Type: GrantFiled: October 17, 2022Date of Patent: May 14, 2024Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
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Publication number: 20240012051Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.Type: ApplicationFiled: August 11, 2023Publication date: January 11, 2024Inventors: Venkata Narayanan Srinivasan, Shiv Kumar Vats, Tripti Gupta
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Patent number: 11835991Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.Type: GrantFiled: March 22, 2021Date of Patent: December 5, 2023Assignee: STMicroelectronics International N.V.Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
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Patent number: 11726140Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.Type: GrantFiled: February 1, 2021Date of Patent: August 15, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Shiv Kumar Vats, Tripti Gupta
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Patent number: 11714131Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.Type: GrantFiled: March 21, 2022Date of Patent: August 1, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Manish Sharma, Shiv Kumar Vats, Umesh Chandra Srivastava
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Patent number: 11680982Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.Type: GrantFiled: October 26, 2021Date of Patent: June 20, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Manish Sharma, Tripti Gupta
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Publication number: 20230168699Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.Type: ApplicationFiled: October 17, 2022Publication date: June 1, 2023Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
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Publication number: 20230128466Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.Type: ApplicationFiled: October 26, 2021Publication date: April 27, 2023Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Manish SHARMA, Tripti GUPTA
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Publication number: 20230105305Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Balwinder Singh SONI, Avneep Kumar GOYAL
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Publication number: 20230042541Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.Type: ApplicationFiled: July 27, 2021Publication date: February 9, 2023Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Balwinder Singh SONI, Avneep Kumar GOYAL
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Patent number: 11557364Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.Type: GrantFiled: July 27, 2021Date of Patent: January 17, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Balwinder Singh Soni, Avneep Kumar Goyal
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Patent number: 11550348Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.Type: GrantFiled: March 24, 2021Date of Patent: January 10, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg
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Patent number: 11513544Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.Type: GrantFiled: November 29, 2021Date of Patent: November 29, 2022Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
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Publication number: 20220308610Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg
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Publication number: 20220300389Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
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Patent number: 11442108Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.Type: GrantFiled: September 16, 2021Date of Patent: September 13, 2022Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Gourav Garg, Dhulipalla Phaneendra Kumar
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Publication number: 20220276302Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Rajesh Narwal, Venkata Narayanan Srinivasan, Srinivas Dhulipalla
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Publication number: 20220244308Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.Type: ApplicationFiled: February 1, 2021Publication date: August 4, 2022Inventors: Venkata Narayanan Srinivasan, Shiv Kumar Vats, Tripti Gupta
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Patent number: 11340292Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.Type: GrantFiled: July 9, 2019Date of Patent: May 24, 2022Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Rajesh Narwal, Venkata Narayanan Srinivasan, Srinivas Dhulipalla
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Patent number: 11119153Abstract: A method of testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by an always on power domain. The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain and an input of the always on domain and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.Type: GrantFiled: May 29, 2020Date of Patent: September 14, 2021Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventor: Venkata Narayanan Srinivasan