Patents by Inventor Venkata Siva Prasad Pulagam
Venkata Siva Prasad Pulagam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11893249Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: GrantFiled: March 9, 2022Date of Patent: February 6, 2024Assignee: Ceremorphic, Inc.Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Anusha Biyyani, Venkatesh Vinjamuri, Shahabuddin Mohammed, Rahul Kumar Gurram, Akhil Soni
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Patent number: 11775306Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.Type: GrantFiled: February 22, 2022Date of Patent: October 3, 2023Assignee: Ceremorphic, Inc.Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkat Mattela, Venkata Siva Prasad Pulagam
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Publication number: 20220206694Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: ApplicationFiled: March 9, 2022Publication date: June 30, 2022Applicant: Ceremorphic, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkata Siva Prasad PULAGAM, Anusha BIYYANI, Venkatesh VINJAMURI, Shahabuddin MOHAMMED, Rahul Kumar GURRAM, Akhil SONI
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Publication number: 20220171629Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.Type: ApplicationFiled: February 22, 2022Publication date: June 2, 2022Applicant: Ceremorphic, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Patent number: 11307779Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: GrantFiled: August 13, 2020Date of Patent: April 19, 2022Assignee: Ceremorphic, Inc.Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Anusha Biyyani, Venkatesh Vinjamuri, Shahabuddin Mohammed, Rahul Kumar Gurram, Akhil Soni
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Patent number: 11288072Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.Type: GrantFiled: August 3, 2020Date of Patent: March 29, 2022Assignee: Ceremorphic, Inc.Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkat Mattela, Venkata Siva Prasad Pulagam
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Publication number: 20210073027Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.Type: ApplicationFiled: August 2, 2020Publication date: March 11, 2021Applicant: Silicon Laboratories Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Publication number: 20210072995Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.Type: ApplicationFiled: August 3, 2020Publication date: March 11, 2021Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Publication number: 20210072906Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: ApplicationFiled: August 13, 2020Publication date: March 11, 2021Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkata Siva Prasad PULAGAM, Anusha BIYYANI, Venkatesh VINJAMURI, Shahabuddin MOHAMMED, Rahul Kumar GURRAM, Akhil SONI
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Publication number: 20210076248Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.Type: ApplicationFiled: August 2, 2020Publication date: March 11, 2021Applicant: Silicon Laboratories Inc.Inventors: Subba Reddy KALLAM, Partha MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Patent number: 10817200Abstract: A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.Type: GrantFiled: October 26, 2017Date of Patent: October 27, 2020Assignee: Silicon Laboratories Inc.Inventors: Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Sailaja Dharani Naga Sankabathula, Venkat Rao Gunturu, Subba Reddy Kallam
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Publication number: 20190129638Abstract: A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy MURALI, Venkata Siva Prasad Pulagam, Sailaja Dharani Naga SANKABATHULA, Venkat Rao Gunturu, Subba Reddy KALLAM