Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements connected between input nodes and a bitline. Each memory element includes a programmable resistor with an input connected to an input node and an output connected to the bitline. Each bank includes a feedback buffer connected to the bitline and an output node. Output nodes of banks in the same column are connected to the same column interconnect line. The initial bank in each row includes amplifiers connected between the input nodes and the memory elements, respectively. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements, each including first and second programmable resistors having inputs connected to an input node and outputs connected to first and second bitlines. In each bank, first and second feedback buffers are connected to the first and second bitlines and first and second output nodes. First and second output nodes of banks in the same column are connected to the same first and second column interconnect lines. The initial bank in each row includes amplifiers connected between the input nodes and memory elements. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing.

Abstract: Disclosed are a structure and method. The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

Abstract: A programmable delay structure includes at least one delay stage, each including an inverter connected between input and output nodes, a threshold voltage (VT)-programmable transistor, and a capacitor connectable to the output node through the transistor. During program mode operations, the transistor is programmed to have a low or high VT. During delay mode operation, the gate voltage is set between the low and high VTs. If the transistor has the low VT, the capacitor is connected to the output node and signal delay is increased. If the transistor has the high VT, the capacitor is not connected to the output node and signal delay is not increased. Illustrated embodiments include additional components for facilitating program mode and delay mode operations. Illustrated embodiments also include multiple delay stages where the output node of one stage is connected to the input node of the next. Also disclosed are associated operating methods.

Abstract: Structures herein include an array of non-volatile memory cells. The non-volatile memory cells include memory bit cells and at least one reference bit cell that is adjacent the memory bit cells. These structures also include at least one reference voltage regulator connected to the reference bit cell, and at least one sense amplifier connected to the memory bit cells and the reference voltage regulator.

Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Abstract: A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.

Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

Abstract: A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.

Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.