Abstract: Techniques for vector unpacking are described. In some examples a single instruction is executed to perform vector unpacking.

Abstract: Techniques for performing an add plus rotation instruction are described. An example of an instruction for performing the add plus rotation is to include one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, and one or more fields for an opcode, the opcode to indicate execution circuitry is to perform addition of data elements of corresponding data element positions of the first and second source operand, wherein data elements of the second source operand are to be positionally rotated prior to the addition according to rotation information and a result of each addition is to be stored in a corresponding data element position of the destination operand.

Abstract: Techniques for conditional loads and/or stores using an instance of a single instruction are described. In some examples, the instance of the single instruction at least includes one or more fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, and one or more fields to reference a destination memory location, wherein the opcode indicates execution circuitry is to conditionally store data elements from data element positions of the second source operand into corresponding data element positions of the memory location of the referenced destination operand based on masking information stored in the referenced first source operand. In some examples, the masking information is provided by a value of a most significant bit position of each data element of the first source operand.

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers and complex conjugates. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply select real and imaginary data elements in the first and second source registers to generate a plurality of real and imaginary products; adder circuitry to add/subtract various real and imaginary products, scale the results according to an immediate of the instruction, round the scaled results; and saturation circuitry to saturate the rounded results.

Abstract: An apparatus and method for performing a vector packed multiplication of signed and unsigned words. For example, one embodiment of a processor includes a decoder to decode a vector packed multiply instruction having operands to identify a first and a second plurality of packed words, first and second source registers to store the first and second plurality of packed words, and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply each packed word in the first source register with a corresponding packed word in the second source register to generate a plurality of doubleword products and rounding circuitry to round each of the doubleword products according to a rounding method to generate a plurality of rounded doubleword products. Each upper word of the rounded doubleword results is then stored into a corresponding word data element positions of a destination register.

Abstract: Apparatus and method for signed and unsigned shift, round and saturate using different data element values.

Abstract: An apparatus and method for multiplying packed unsigned words.

Abstract: Methods and apparatus relating to speculatively decoding instruction lengths in order to increase instruction throughput are described. In an embodiment, instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles. Other embodiments are also disclosed.

Abstract: Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder buffer. The sequencer is to issue micro-operations. The reorder buffer is to signal the sequencer to signal the sequencer to issue micro-operations corresponding to a monitor trap flag event.

Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

Abstract: A method and an apparatus for decoding a variable length instruction. The method includes selecting with a first pointer one of a plurality of permutations, each permutation representing a possible location of the instruction in a portion of the datastream, calculating a possible length of the instruction for each byte in the selected permutation, and selecting the length of the instruction from one of the calculated possible lengths in the selected permutation. An example of an application includes decoding X86 instruction formats.

Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

Abstract: A system for debugging a processor includes a debug interface including a handshake logic for communicating commands and data from a serial input/output port to a processor and to a trace control logic with a low delay. The handshake logic results in a low latency through the inclusion of a state machine that operates at the same speed as the processor. The state machine generates handshake signals to communicate among the serial input/output port, the processor, and the trace control logic.

Abstract: A system for debugging a processor includes logic circuits for communicating commands and data between a serial input/output port, a trace logic, and the processor. Some embodiments of the debugging system also include a parallel input/output port so that the logic circuits also communicate commands and data between the parallel input/output port, the trace logic, and the processor. The debug system includes a plurality of state machines that read the commands and data from the serial input/output ports. The commands are decoded by a decode logic. Some of the commands, such as commands for reading data from memory, utilize processor intervention and are transferred to the processor for execution. The state machines operate only on a single command at one time so that an active state machine does not accept additional commands until completion of the command that is currently executed.

Abstract: A system for debugging a processor includes a logic circuit for communicating commands and data between an input/output port which operates at a first clock frequency, and trace control logic which operates at a second clock frequency that is different from the first clock frequency. In some embodiments, the input/output port is a JTAG (Joint Test Action Group) port operating at a maximum clock frequency of 25 MHz and the trace control logic operates at a clock frequency of 33 Mhz, 66 MHz, 99 MHz, or 133 mhz. A suitable JTAG clock frequency is a minimum of either half the CPU internal clock frequency or 2.25 Mhz for synchronizing the internal signals between different clock frequencies. When the input/output port, which is typically a serial/parallel input/output port, writes data to debug registers, including ITCR, DCSR, soft.sub.-- address, and RX.sub.

Abstract: A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.