Abstract: Disclosed examples include a method. The method includes: conveying symbols from a PHY toward a MAC via a PHY-side of PHY-MAC interface; and filtering one or more symbols at an input of a PHY-side of an interface wrapper of the PHY-side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY-side of PHY-MAC interface; and a logic circuit provided at the PHY-side of PHY-MAC interface, the logic circuit comprising a symbol filter to filter one or more symbols conveyed via the PHY-side of PHY-MAC interface.

Abstract: An apparatus may include a physical layer device, a detection circuitry and a power control circuitry. the physical layer device provides one or more functions of a physical layer to interface with a shared physical transmission medium. The detection circuitry detects an indication of power control signaling on the shared physical transmission medium, and detects an indication of Ethernet signaling on the shared physical transmission medium. The indication of power control signaling is different than the indication of Ethernet signaling. The power control circuitry manages a power state of the apparatus at least partially responsive to an output of the detection circuitry.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.

Abstract: Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.

Abstract: Disclosed embodiments relate, generally, to improved data reception handling at a physical layer (PHY). Some embodiments relate to end of line systems that include legacy media access control (MAC) and PHY that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of the end of line systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Abstract: On or more examples relate, generally, to an apparatus that includes a reconciliation sublayer of a physical layer, a reduced media independent interface (RMII) of the physical layer, and a logic circuit. Such a logic circuit may operate to receive a changed carrier sense signal provided by the reconciliation sublayer, generate a further changed carrier sense signal at least partially responsive to a prediction that the changed carrier sense signal would cause unintended signaling at the RMII, and provide the further changed carrier sense signal to the RMII.

Abstract: One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: Sensors, imaging systems, and methods for forming a sensor with a specified depth profile are provided. One sensor includes a substrate and one or more components attached to the substrate. The sensor also includes a sensor die having a thinned backside and energy sensitive elements configured for detecting energy illuminating the thinned backside of the sensor die. The sensor further includes discrete thermally-conductive structures formed between a frontside of the sensor die and the substrate by a flip-chip process thereby bonding the sensor die to the substrate and causing the thinned backside of the sensor die to have a pre-selected shape. At least a portion of the discrete thermally-conductive structures electrically connect the sensor die to the one or more components.

Abstract: Disclosed are systems and devices for interfacing media access tuning circuitry that implements collision handling or traffic shaping with a reduced media independent interface (RMII). In some embodiments, an interface circuitry manages emulated signals generated by a media access tuning circuitry in response to detecting that the emulated signals would cause incorrect operation of an RMII. Also disclosed is a physical layer (PHY) device for a multidrop network. In some embodiments the PHY device implements physical layer collision techniques and operable to communicate with a media access control (MAC) device via an RMII, where the MAC is configured for carrier-sense multiple access (CSMA), CSMA with collision detection (CSMA/CD), or CSMA with collision avoidance (CSMA/CA). Also disclosed are processes for managing signaling at a PHY that implements physical layer collision avoidance (PLCA) or traffic shaping, as the case may be.

Abstract: Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface.

Abstract: Various examples relate to a wired local area network (WLAN) including a shared transmission medium. An apparatus includes a beacon counter and an operational mode controller. The beacon counter is operably coupled to a line of a shared transmission medium of a wired local area network. The beacon counter is to count beacon signals on the line and determine a beacon count over a predetermined time period, or a beacon rate of the beacon signals. The operational mode controller is to control the apparatus to take over operation as a master node of the wired local area network based, at least in part, on a maximum bus cycle length of bus cycles on the line and responsive to the beacon count or the beacon rate.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Abstract: An electronic apparatus and method of controlling the electronic apparatus are provided. The electronic apparatus includes a communicator, a storage storing information on places wherein Internet of Things (IoT) devices are located, and a processor configured to, based on receiving a control signal for controlling an IoT device located in a specific place through the communicator, control the IoT device located in the specific place based on information on the place stored in the storage. The processor is further configured to receive motion information generated based on a motion of a wearable device from the wearable device, identify a place corresponding to the motion information, and store the identified place as information on a place of an IoT device located within a predetermined distance from the wearable device, in the storage.