Patents by Inventor Venugopal Vellanki
Venugopal Vellanki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11460784Abstract: A method of determining candidate patterns from a set of patterns of a patterning process. The method includes obtaining (i) a set of patterns of a patterning process, (ii) a search pattern having a first feature and a second feature, and (iii) a search condition comprising a relative position between the first feature and the second feature of the search pattern; and determining a set of candidate patterns from the set of patterns that satisfies the search condition associated with the first feature and the second feature of the search pattern.Type: GrantFiled: September 20, 2019Date of Patent: October 4, 2022Assignee: ASML Netherlands B.V.Inventors: Venugopal Vellanki, Mark Christopher Simmons
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Publication number: 20220147665Abstract: A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.Type: ApplicationFiled: January 28, 2022Publication date: May 12, 2022Applicant: ASML NETHERLANDS B.V.Inventors: Stefan Hunsche, Venugopal Vellanki
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Patent number: 11238189Abstract: A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.Type: GrantFiled: June 4, 2018Date of Patent: February 1, 2022Assignee: ASML Netherlands B.V.Inventors: Stefan Hunsche, Venugopal Vellanki
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Patent number: 11176307Abstract: A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.Type: GrantFiled: November 13, 2017Date of Patent: November 16, 2021Assignee: ASML Netherlands B.V.Inventors: Venugopal Vellanki, Been-Der Chen
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Publication number: 20210325786Abstract: A method of determining candidate patterns from a set of patterns of a patterning process. The method includes obtaining (i) a set of patterns of a patterning process, (ii) a search pattern having a first feature and a second feature, and (iii) a search condition comprising a relative position between the first feature and the second feature of the search pattern; and determining a set of candidate patterns from the set of patterns that satisfies the search condition associated with the first feature and the second feature of the search pattern.Type: ApplicationFiled: September 20, 2019Publication date: October 21, 2021Applicant: ASML NETHERLANDS B.V.Inventors: Venugopal VELLANKI, Mark Christopher SIMMONS
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Publication number: 20210255548Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.Type: ApplicationFiled: May 6, 2021Publication date: August 19, 2021Applicant: ASML Netherlands B.V.Inventors: Venugopal VELLANKI, Vivek Kumar JAIN, Stefan HUNSCHE
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Patent number: 11003093Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including; determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.Type: GrantFiled: November 26, 2019Date of Patent: May 11, 2021Assignee: ASML Netherlands B.V.Inventors: Venugopal Vellanki, Vivek Kumar Jain, Stefan Hunsche
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Publication number: 20200193080Abstract: A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.Type: ApplicationFiled: November 13, 2017Publication date: June 18, 2020Applicant: ASML NETHERLANDS B.V.Inventors: Venugopal VELLANKI, Been-Der CHEN
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Publication number: 20200096871Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including; determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Applicant: ASML Netherlands B.V.Inventors: Venugopal VELLANKI, Vivek Kumar JAIN, Stefan HUNSCHE
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Patent number: 10514614Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.Type: GrantFiled: January 20, 2016Date of Patent: December 24, 2019Assignee: ASML Netherlands B.V.Inventors: Venugopal Vellanki, Vivek Kumar Jain, Stefan Hunsche
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Publication number: 20180330030Abstract: A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.Type: ApplicationFiled: June 4, 2018Publication date: November 15, 2018Applicant: ASML NETHERLANDS B.V.Inventors: Stefan HUNSCHE, Venugopal Vellanki
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Publication number: 20180031981Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.Type: ApplicationFiled: January 20, 2016Publication date: February 1, 2018Applicant: ASML Netherlands B.V.Inventors: Venugopal VELLANKI, Vivek Kumar JAIN, Stefan HUNSCHE
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Patent number: 9459537Abstract: The present invention discloses various system and process embodiments where wafer-metrology and direct measurements of the lithography apparatus characteristics are combined to achieve temporal drift reduction in a lithography apparatus/process using a simulation model. The simulation model may have sub-components. For example, a sub-model may represent a first set of optical conditions, and another sub-model may represent a second set of optical conditions. The first set of optical conditions may be a standard set of illumination conditions, and the second set may be a custom set of illumination conditions. Using the inter-relationship of the sub-models, stability control under custom illumination condition can be achieved faster without wafer metrology.Type: GrantFiled: June 21, 2012Date of Patent: October 4, 2016Assignee: ASML NETHERLANDS B.V.Inventors: Yu Cao, Jun Ye, Venugopal Vellanki, Johannes Catharinus Hubertus Mulkens
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Publication number: 20120327383Abstract: The present invention discloses various system and process embodiments where wafer-metrology and direct measurements of the lithography apparatus characteristics are combined to achieve temporal drift reduction in a lithography apparatus/process using a simulation model. The simulation model may have sub-components. For example, a sub-model may represent a first set of optical conditions, and another sub-model may represent a second set of optical conditions. The first set of optical conditions may be a standard set of illumination conditions, and the second set may be a custom set of illumination conditions. Using the inter-relationship of the sub-models, stability control under custom illumination condition can be achieved faster without wafer metrology.Type: ApplicationFiled: June 21, 2012Publication date: December 27, 2012Applicant: ASML Netherlands B.V.Inventors: Yu Cao, Jun Ye, Venugopal Vellanki, Johannes Catharinus Hubertus Mulkens