Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

Abstract: A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.

Abstract: An example memory cell may have at least a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region can have at least an active interface regio disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state.

Abstract: A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.

Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

Abstract: A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.

Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.

Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.