Patents by Inventor Vern H. Winchell, II

Vern H. Winchell, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5886362
    Abstract: An integrated circuit die is tested by inserting test probe needles into flat solder pads before reflow. The testing is performed at different temperatures to functionally test the integrated circuit die. The solder pads are flat during probe test to improve the uniform contact point and pressure for the test probes, and help avoid slippage or sliding. The probe needles may cause indentation in the solder pads. Following probe test, the solder pads are reflowed to transform the solder pads into solder bumps. Reflow after probe test removes any indentations from the solder pads created during the probe test and leaves only rounded solder bumps without probe damage. The solder bumps are used to flip-chip interconnect the IC into end user systems.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Lavoie R. Millican, Vern H. Winchell, II
  • Patent number: 5164885
    Abstract: A non-oxide ceramic (16) for electronic packages and a method of producing electronic packages using a non-oxide ceramic is provided. In accordance with the present invention, the non-oxide ceramic (16) is coated with silicon dioxide (15) and a bonding glass (14) having diboron trioxide is used to attach other package components such as semiconductor chips (18), leadframes (13), and heatsinks (11) to the non-oxide ceramic (16).
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: November 17, 1992
    Assignee: Motorola, Inc.
    Inventors: James E. Drye, David J. Reed, Vern H. Winchell, II
  • Patent number: 4722914
    Abstract: An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metalization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.
    Type: Grant
    Filed: August 13, 1986
    Date of Patent: February 2, 1988
    Assignee: Motorola Inc.
    Inventors: James E. Drye, Jack A. Schroeder, Vern H. Winchell, II
  • Patent number: 4630096
    Abstract: An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metallization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.
    Type: Grant
    Filed: May 30, 1984
    Date of Patent: December 16, 1986
    Assignee: Motorola, Inc.
    Inventors: James E. Drye, Jack A. Schroeder, Vern H. Winchell, II
  • Patent number: 4609936
    Abstract: Structure and process for providing a hard metallic leadframe directly bonded to a semiconductor chip without the necessity for solder or soft intermediate leadframes. The structure provides a strong bond at the semiconductor chip with the possibility for multiple simultaneous lead attachment of a leadframe having sufficient strength to serve as the external leads. The bonded structure may be conventionally encapsulated in a plastic or ceramic package, or may be glassed to provide a minimum volume hermetic chip.
    Type: Grant
    Filed: September 19, 1979
    Date of Patent: September 2, 1986
    Assignee: Motorola, Inc.
    Inventors: Thomas A. Scharr, Vern H. Winchell, II
  • Patent number: 4394678
    Abstract: An elevated bonding pad suitable for wire or lead frame attachment and having an insulating layer completely over its outer periphery. The structure simplifies the processing required to form an elevated bonding pad, and serves to protect the periphery against bonding damage, and provides protection against corrosion of the bonded encapsulated semiconductor unit.
    Type: Grant
    Filed: September 19, 1979
    Date of Patent: July 19, 1983
    Assignee: Motorola, Inc.
    Inventors: Vern H. Winchell, II, Thomas A. Scharr, Lowell E. Clark