Patents by Inventor Verne Hornback
Verne Hornback has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8384165Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.Type: GrantFiled: June 17, 2008Date of Patent: February 26, 2013Assignee: LSI CorporationInventors: Richard J. Carter, Wai Lo, Sey-Shing Sun, Hong Lin, Verne Hornback
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Patent number: 7915122Abstract: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer.Type: GrantFiled: December 20, 2005Date of Patent: March 29, 2011Assignee: Nantero, Inc.Inventors: Richard J. Carter, Hemanshu D. Bhatt, Shiqun Gu, Peter A. Burke, James R. B. Elmer, Sey-Shing Sun, Byung-Sung Kwak, Verne Hornback
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Publication number: 20080308882Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.Type: ApplicationFiled: June 17, 2008Publication date: December 18, 2008Applicant: LSI CORPORATIONInventors: Richard J. Carter, Wai Lo, Sey-Shing Sun, Hong Lin, Verne Hornback
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Patent number: 7405116Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.Type: GrantFiled: August 11, 2004Date of Patent: July 29, 2008Assignee: LSI CorporationInventors: Richard J. Carter, Wai Lo, Sey-Shing Sun, Hong Lin, Verne Hornback
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Patent number: 7312127Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.Type: GrantFiled: March 23, 2006Date of Patent: December 25, 2007Assignee: LSI CorporationInventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
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Patent number: 7189628Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.Type: GrantFiled: August 31, 2004Date of Patent: March 13, 2007Assignee: LSI Logic CorporationInventors: Mohammad R. Mirbedini, Venkatesh P. Gopinath, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le
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Publication number: 20060281256Abstract: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer.Type: ApplicationFiled: December 20, 2005Publication date: December 14, 2006Inventors: Richard Carter, Hemanshu Bhatt, Shiqun Gu, Peter Burke, James Elmer, Sey-Shing Sun, Byung-Sung Kwak, Verne Hornback
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Publication number: 20060166496Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.Type: ApplicationFiled: March 23, 2006Publication date: July 27, 2006Inventors: Wai Lo, Verne Hornback, Wilbur Catabay, Wei-Jen Hsia, Sey-Shing Sun
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Patent number: 7064062Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.Type: GrantFiled: December 16, 2003Date of Patent: June 20, 2006Assignee: LSI Logic CorporationInventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
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Publication number: 20060035425Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.Type: ApplicationFiled: August 11, 2004Publication date: February 16, 2006Inventors: Richard Carter, Wai Lo, Sey-Shing Sun, Hong Lin, Verne Hornback
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Publication number: 20050127458Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.Type: ApplicationFiled: December 16, 2003Publication date: June 16, 2005Inventors: Wai Lo, Verne Hornback, Wilbur Catabay, Wei-Jen Hsia, Sey-Shing Sun
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Patent number: 6864152Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.Type: GrantFiled: May 20, 2003Date of Patent: March 8, 2005Assignee: LSI Logic CorporationInventors: Mohammad R. Mirbedini, Venkatesh P. Gopinath, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le
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Patent number: 6355532Abstract: A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically.Type: GrantFiled: October 6, 1999Date of Patent: March 12, 2002Assignee: LSI Logic CorporationInventors: John J. Seliskar, Verne Hornback, David Daniel
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Patent number: 6071562Abstract: The present invention provides an efficient process for depositing a titanium nitride film on a substrate. The process comprises the steps of heating the substrate and subsequently exposing the heated substrate to a first gas containing tetrakis(dimethylamido)titanium and to a second gas containing tetrakis(diethylamido)titanium.Type: GrantFiled: May 7, 1998Date of Patent: June 6, 2000Assignee: LSI Logic CorporationInventors: Verne Hornback, Derryl Allman