Abstract: The claimed embodiments contemplate methods, systems and apparatuses directed to an active display button. In various embodiments, an active display button may generally be a button containing one or more elements that move when the button is engaged. By example, and not limitation, these elements may include one or more reels, be they mechanical or video, or perhaps a rotating indicator. The active display button may also include lights, vibratory motors and other experience-enhancing implements. The active display button may be installed on a gaming machine and operated in conjunction with the gaming device, separate from the gaming machine on which it is installed or perhaps as part of the operation of the gaming machine.

Abstract: A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the I/O coprocessor (38) are coupled to the peripheral bus (32). The I/O coprocessor (38) has a plurality of front-end channels (50) for receiving a time-base, and in response, for providing a time-base reference for input signals and generating output signals using the time-base reference. A back-end processor (80) controls operation of the plurality of front-end channels (50) in response to executing instructions. A visibility bus (40), coupled to the back-end processor (80), is for providing visibility of the internal registers of the back-end processor (80) independent of the CPU (20). The visibility is provided for development of the instructions executed by the back-end processor (80).

Abstract: I/O control modules (25-29) include a timer bus (71, 72) which may be segmented anywhere along its length. As a result, the channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebases by their respective timer bus (71, 72). The channels within one timer bus block (e.g. 86) can be used to perform different function(s) with the potential for no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). In one embodiment, one end of each timer bus (71, 72) is delineated by a master timer bus control channel (61, 63), and the other end of the timer bus is delineated by a slave timer bus control channel (62, 64).

Abstract: Timebase channels in different I/O control modules (IOCMs 281-284 in FIG. 16) or on different integrated circuits (300-302 in FIG. 17 ) may provide synchronized, coherent timebase values to different blocks of work and other channels (e.g. 86 in FIG. 2) that are coupled to different timer buses (e.g. 71 in FIG. 2). In one embodiment, referring to FIGS. 1-19, two or more timebase channels, e.g. master timebase channel (285) and slave timebase channel (288), can be synchronized and kept in synchronization using just two signals, namely a clock signal (328) and a synchronization signal (329). The master timebase channel (285) generates or receives a master dock signal (328) which is coupled to one or more slave timebase channels (288) to ensure that the master and slave timebase channels (285, 288) increment or decrement at the same time and rate.

Abstract: I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Thus, the operation of channels (e.g. 58) can be synchronized with each another. Pin/status buses (75-77) are modular in that they can be extended or alternately segmented to create separate buses carrying different signals. In one embodiment, each end of pin/status bus (75-77) is delineated by a pin control channel (PCCs 51-53). Pin/status buses (75-77) may be used to transfer event information between channels within an IOCM (e.g. IOCM 25), to transfer event information from one IOCM (e.g. 25) to a different IOCM (e.g. 26), and to transfer pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29).

Abstract: An improved spray head for a nozzle for atomizing a liquid with a gas has an open inner end to receive the gas and liquid, a cylindrical medial portion defining a mixing chamber for creating a liquid-gas mixture, and an outer end wall that has a plurality of orifices arranged in a spaced circular orientation about the longitudinal axis of the mixing chamber. Each orifice defines a flow axis which is directed toward a linear target located a predetermined distance from the spray head for atomizing and directing a respective portion of the liquid-gas mixture onto the linear target in an approximately planar, flat fan spray pattern. A liquid atomizer is coupled in fluid communication between an inlet conduit for the liquid and the mixing chamber for atomizing the liquid discharged into the mixing chamber and creating the liquid-gas mixture.