Patents by Inventor Veronica S. Davila
Veronica S. Davila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11307900Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.Type: GrantFiled: January 16, 2020Date of Patent: April 19, 2022Assignee: International Business Machines CorporationInventors: Veronica S. Davila, Trung N. Nguyen, Louis A. Rasor
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Patent number: 10956148Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: November 14, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20200151012Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventors: Veronica S. Davila, Trung N. Nguyen, Louis A. Rasor
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Publication number: 20200081702Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10565020Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.Type: GrantFiled: August 29, 2017Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veronica S. Davila, Trung N. Nguyen, Louis A. Rasor
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Patent number: 10540170Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: September 12, 2018Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20190065257Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: Veronica S. Davila, Trung N. Nguyen, Louis A. Rasor
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Publication number: 20190012165Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: September 12, 2018Publication date: January 10, 2019Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 10114633Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: December 8, 2016Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Publication number: 20180165082Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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Patent number: 9886070Abstract: A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will be powered off after a predetermined amount of time. The storage controller quiesces all I/O adapters of the I/O enclosure, in response to receiving the indication. The storage controller quiesces the I/O enclosure, in response to completion of quiescing of all of the I/O adapters of the I/O enclosure.Type: GrantFiled: November 20, 2015Date of Patent: February 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herve G. P. Andre, Gary W. Batchelor, Scott A. Brewer, Veronica S. Davila, Enrique Q. Garcia, Daniel I. Ibanez, Trung N. Nguyen, Louis A. Rasor, Brian A. Rinaldi, Micah Robison, Todd C. Sorenson
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Publication number: 20170147049Abstract: A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will be powered off after a predetermined amount of time. The storage controller quiesces all I/O adapters of the I/O enclosure, in response to receiving the indication. The storage controller quiesces the I/O enclosure, in response to completion of quiescing of all of the I/O adapters of the I/O enclosure.Type: ApplicationFiled: November 20, 2015Publication date: May 25, 2017Inventors: Herve G. P. Andre, Gary W. Batchelor, Scott A. Brewer, Veronica S. Davila, Enrique Q. Garcia, Daniel I. Ibanez, Trung N. Nguyen, Louis A. Rasor, Brian A. Rinaldi, Micah Robison, Todd C. Sorenson
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Patent number: 7783931Abstract: An enterprise network interface client application and a local, central electronic complex (CEC) in a dual CEC environment implement an alternative method of communication. Upon a send failure of a command to a first CEC in the environment, the command is sent to a second CEC using a CEC to CEC message mechanism. A method of communicating an asynchronous event is implemented between a microcode layer and an enterprise network interface client application in a dual central electronic complex (CEC) environment. A copy of the event is retained. Upon a send failure of the event to a first CEC in the environment, the copy of the event is sent to a second CEC in the environment.Type: GrantFiled: May 4, 2007Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Juan A. Coronado, Veronica S. Davila, Jack N. Licano, Jr., Brian S. McCain, Beth A. Peterson
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Publication number: 20080276255Abstract: An enterprise network interface client application and a local, central electronic complex (CEC) in a dual CEC environment implement an alternative method of communication. Upon a send failure of a command to a first CEC in the environment, the command is sent to a second CEC using a CEC to CEC message mechanism. A method of communicating an asynchronous event is implemented between a microcode layer and an enterprise network interface client application in a dual central electronic complex (CEC) environment. A copy of the event is retained. Upon a send failure of the event to a first CEC in the environment, the copy of the event is sent to a second CEC in the environment.Type: ApplicationFiled: May 4, 2007Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juan A. Coronado, Veronica S. Davila, Jack N. Licano, Brian S. McCain, Beth A. Peterson