Patents by Inventor Viacheslav DUBEYKO
Viacheslav DUBEYKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200311200Abstract: In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200293223Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200293222Abstract: A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200257562Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Patent number: 10740231Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. Data smaller than a smallest writable unit of the secondary memory is accessed in the SCM based on an instruction from the processor. In another aspect, unique identifiers are calculated for portions of data to be stored in the secondary memory using the portions of data. A mapping of the unique identifiers is stored with indications of physical locations where the corresponding portions of data are stored in the secondary memory. In yet another aspect, an operation instruction is received from the processor, and data is loaded from the secondary memory into the SCM for performing the operation.Type: GrantFiled: November 20, 2018Date of Patent: August 11, 2020Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Chao Sun
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Publication number: 20200159659Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. Data smaller than a smallest writable unit of the secondary memory is accessed in the SCM based on an instruction from the processor. In another aspect, unique identifiers are calculated for portions of data to be stored in the secondary memory using the portions of data. A mapping of the unique identifiers is stored with indications of physical locations where the corresponding portions of data are stored in the secondary memory. In yet another aspect, an operation instruction is received from the processor, and data is loaded from the secondary memory into the SCM for performing the operation.Type: ApplicationFiled: November 20, 2018Publication date: May 21, 2020Inventors: Viacheslav Dubeyko, Chao Sun
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Publication number: 20200151020Abstract: A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array. Each of the first data processing unit and the other data processing units include a dedicated non-volatile memory. The system and method also include receiving, by the first data processing unit, a code of execution results from each of the other data processing units that execute the user request, combining, by the first data processing unit, the code of execution results from the each of the other data processing units that execute the user request, and responding, by the first data processing unit, to the user request by transmitting the combined code of execution results.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Viacheslav Dubeyko, Luis Vitório Cargnini
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Patent number: 10606513Abstract: A Memory Device (MD) includes a configurable Non-Volatile Memory (NVM) including a first memory array and a second memory array. The configurable NVM stores temporary data designated for volatile storage by a Central Processing Unit (CPU) and persistent data designated for non-volatile storage by the CPU. An address is associated with a first location in the first memory array and with a second location in the second memory array. In performing a command to write data for the address, it is determined whether to write the data in the second location based on a volatility mode set for the MD. According to another aspect, a CPU designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.Type: GrantFiled: December 6, 2017Date of Patent: March 31, 2020Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Cargnini
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Publication number: 20200089435Abstract: A Memory Device (MD) includes a Non-Volatile Memory (NVM) including a first memory array and a second memory array. An address is associated with a first location in the first memory array and with a second location in the second memory array. A read command is received to read data for the address, and it is determined whether data stored in the NVM for the address is persistent. If not, it is determined whether data for the address has been written for the address after a last power-up of the MD. The read command is performed by returning zeroed data if data has not been written for the address after the last power-up. If data has been written after the last power-up, data stored in the first location is returned. In one aspect, a processor sends a command to the MD setting a volatility mode for the MD.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Inventors: Viacheslav Dubeyko, Luis Cargnini
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Patent number: 10521148Abstract: A Data Storage Device (DSD) includes a memory and a non-volatile storage. Data related to one or more write requests is received in a write buffer of the memory from a host to modify a file system volume stored in a file system volume area of the non-volatile storage. The data related to the one or more write requests is de-staged into the file system volume area in at least one block to be modified in the file system volume by the one or more write requests. The data related to the one or more write requests is compiled into a backup slice in a backup buffer of the memory, and de-staged into a backup archive area of the non-volatile storage.Type: GrantFiled: March 7, 2018Date of Patent: December 31, 2019Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Adam Manzanares
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Publication number: 20190377607Abstract: A processor includes processor memory arrays including one or more volatile memory arrays and one or more Non-Volatile Memory (NVM) arrays. Volatile memory locations in the one or more volatile memory arrays are paired with respective NVM locations in the one or more NVM arrays to form processor memory pairs. Process data is stored for different processes executed by at least one core of the processor in respective processor memory pairs. Processes are executed using the at least one core to directly access the process data stored in the respective processor memory pairs.Type: ApplicationFiled: June 6, 2018Publication date: December 12, 2019Inventors: Viacheslav Dubeyko, Luis Cargnini
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Publication number: 20190354517Abstract: System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.Type: ApplicationFiled: July 26, 2019Publication date: November 21, 2019Inventors: Viacheslav DUBEYKO, Adam MANZANARES
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Publication number: 20190317920Abstract: A verification architecture described according to embodiments of the present invention validates changes made to metadata and may comprise one or more subsystems and phases. According to some embodiments, the “mkfs” volume creation utility works in cooperation with the device driver to create a file system volume by means of reservation and initialization space for metadata structures inside the device's partition that is reserved for the specific file system volume. The storage device uses a verified area legend when checking write requests after the file system volume has been created. The verified area legends may be stored in a dedicated partition or inside the master boot record (MBR) or Globally Unique Identifier (GUID) partition table (GPT) or special memory chip (NAND flash, for example). Write requests that overlap with any extent of reserved metadata area must be verified to prevent metadata corruption.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Inventors: Viacheslav DUBEYKO, Adam MANZANARES
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Publication number: 20190286325Abstract: A Memory Device (MD) for storing temporary data designated for volatile storage by a processor and persistent data designated for non-volatile storage by the processor. An address is associated with a first location in a volatile memory array and with a second location in a Non-Volatile Memory (NVM) array of the MD. Data is written in the first location, and flushed from the first location to the second location. A refresh rate for the first location is reduced after flushing the data from the first location until after data is written again to the first location. In another aspect, a processor designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Viacheslav Dubeyko, Luis Cargnini
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Publication number: 20190278482Abstract: A Data Storage Device (DSD) includes a memory and a non-volatile storage. Data related to one or more write requests is received in a write buffer of the memory from a host to modify a file system volume stored in a file system volume area of the non-volatile storage. The data related to the one or more write requests is de-staged into the file system volume area in at least one block to be modified in the file system volume by the one or more write requests. The data related to the one or more write requests is compiled into a backup slice in a backup buffer of the memory, and de-staged into a backup archive area of the non-volatile storage.Type: ApplicationFiled: March 7, 2018Publication date: September 12, 2019Inventors: Viacheslav Dubeyko, Adam Manzanares
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Patent number: 10380069Abstract: A verification architecture described according to embodiments of the present invention validates changes made to metadata and may comprise one or more subsystems and phases. According to some embodiments, the “mkfs” volume creation utility works in cooperation with the device driver to create a file system volume by means of reservation and initialization space for metadata structures inside the device's partition that is reserved for the specific file system volume. The storage device uses a verified area legend when checking write requests after the file system volume has been created. The verified area legends may be stored in a dedicated partition or inside the master boot record (MBR) or Globally Unique Identifier (GUID) partition table (GPT) or special memory chip (NAND flash, for example). Write requests that overlap with any extent of reserved metadata area must be verified to prevent metadata corruption.Type: GrantFiled: May 4, 2016Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Adam Manzanares
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Patent number: 10380100Abstract: System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.Type: GrantFiled: April 27, 2016Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Adam Manzanares
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Publication number: 20190171391Abstract: A Memory Device (MD) includes a configurable Non-Volatile Memory (NVM) including a first memory array and a second memory array. The configurable NVM stores temporary data designated for volatile storage by a Central Processing Unit (CPU) and persistent data designated for non-volatile storage by the CPU. An address is associated with a first location in the first memory array and with a second location in the second memory array. In performing a command to write data for the address, it is determined whether to write the data in the second location based on a volatility mode set for the MD. According to another aspect, a CPU designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Inventors: Viacheslav Dubeyko, Luis Cargnini
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Patent number: 10310925Abstract: Metadata area legends are stored at a first location, such as a dedicated partition of a persistent data storage device (PDSD). The metadata area legends have a number of descriptors that describe a number of reserved metadata areas that lie at a second location that is logically separate from the first location, such as a regular partition of the PDSD. Requests to delete the metadata area legends, as well as requests to add new metadata area legends, can be verified to prevent the metadata area legends from being accidentally or maliciously changed.Type: GrantFiled: March 2, 2016Date of Patent: June 4, 2019Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Adam Manzanares
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Patent number: 10067683Abstract: Systems and methods for writing data to a storage are disclosed. The disclosed systems and methods can receive, by a target device in communication with a host, a first write request from the host to write first data to the storage in communication with the target device. The disclosed systems and methods can determine, by a storage controller in the target device, a data type of the first data based on a first flag set corresponding to the first data. The disclosed systems and methods can store the first data to a location in the storage based at least on the data type of the first data.Type: GrantFiled: July 19, 2016Date of Patent: September 4, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Viacheslav Dubeyko, Chao Sun