Patents by Inventor Vic Alfano
Vic Alfano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8913618Abstract: There are disclosed processes and apparatus for reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: GrantFiled: December 27, 2011Date of Patent: December 16, 2014Assignee: Bunson Bell, Limited Liability CompanyInventor: Vic Alfano
-
Publication number: 20120093162Abstract: There are disclosed processes and apparatus for reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: ApplicationFiled: December 27, 2011Publication date: April 19, 2012Applicant: BUNSON BELL, LLCInventor: Vic Alfano
-
Patent number: 8107377Abstract: There are disclosed processes and apparatus for reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: GrantFiled: April 13, 2010Date of Patent: January 31, 2012Assignee: Bunson Bell, LLCInventor: Vic Alfano
-
Patent number: 7856011Abstract: There are disclosed processes and apparatus reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: GrantFiled: September 27, 2005Date of Patent: December 21, 2010Inventor: Vic Alfano
-
Publication number: 20100189123Abstract: There are disclosed processes and apparatus for reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: ApplicationFiled: April 13, 2010Publication date: July 29, 2010Inventor: Vic Alfano
-
Patent number: 7590721Abstract: System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.Type: GrantFiled: June 6, 2007Date of Patent: September 15, 2009Assignee: Topside Research, LLCInventor: Vic Alfano
-
Publication number: 20070237151Abstract: System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.Type: ApplicationFiled: June 6, 2007Publication date: October 11, 2007Inventor: Vic Alfano
-
Publication number: 20060072578Abstract: There are disclosed processes and apparatus reordering packets. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: ApplicationFiled: September 27, 2005Publication date: April 6, 2006Inventor: Vic Alfano
-
Patent number: 6967951Abstract: System for reordering sequenced based packets in a switching network. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An Enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A Dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: GrantFiled: January 11, 2002Date of Patent: November 22, 2005Assignee: Internet Machines Corp.Inventor: Vic Alfano
-
Publication number: 20040098509Abstract: System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.Type: ApplicationFiled: November 14, 2002Publication date: May 20, 2004Inventor: Vic Alfano
-
Publication number: 20030133465Abstract: System for reordering sequenced based packets in a switching network. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An Enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A Dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.Type: ApplicationFiled: January 11, 2002Publication date: July 17, 2003Inventor: Vic Alfano