Abstract: Adaptive bandwidth management systems and methods are disclosed. An exemplary system comprises a network switching device including a plurality of physical ports and at least one switching fabric for managing connections between the physical ports. The system also includes a management processor operatively associated with the plurality of physical ports and the at least one switching fabric. The system also includes program code stored in computer-readable storage and executable by the management processor, the program code configuring the network switching device to conserve electrical energy based on the current bandwidth requirements.

Abstract: A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of trailing zeros. The method includes generating a first remainder based on the sub-message data and a first factor of the CRC generating polynomial. A second remainder is generated based on the sub-message data and a second factor of the CRC generating polynomial. The CRC for the composite sub-message is generated based on adjusted versions of the first and the second remainders.

Abstract: A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a desired pattern of intermediate CRC values. The method includes generating a test data pattern based on the desired pattern of intermediate CRC values and the generator polynomial, wherein the test data pattern is configured to cause the CRC algorithm to generate the desired pattern of intermediate CRC values.

Abstract: Methods for adjusting an m-bit CRC of sub-messages are provided. Such adjustments enable the computation of the CRC of a message by XORing the partial or incremental CRCs of composite sub-messages corresponding to the sub-messages. In a first method, the contents of an m-bit memory location are field squared and stepped to the next state as determined by the Galois field generated by the CRC generating polynomial to adjust the m-bit CRC. In a second method, the partial m-bit CRC of a sub-message is calculated according to CRC generating polynomial, P(x). A variable Y is calculated using a lookup table, where Y=xn modulo P(x). The partial m-bit CRC and Y are multiplied together and divided by P(x). The remainder of the division forms the adjusted m-bit CRC.

Abstract: A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words, with each word including a plurality of bytes. Each of the lookup tables stores a plurality of multi-byte CRC values. The system includes a processor for processing the message a word at a time. The processor is configured to update the current CRC value during processing each word based on an XOR of the word and the current CRC value, and based on a multi-byte CRC value retrieved from each one of the lookup tables.

Abstract: A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of trailing zeros. The method includes generating a first remainder based on the sub-message data and a first factor of the CRC generating polynomial. A second remainder is generated based on the sub-message data and a second factor of the CRC generating polynomial. The CRC for the composite sub-message is generated based on adjusted versions of the first and the second remainders.

Abstract: Methods for adjusting an m-bit CRC of sub-messages are provided. Such adjustments enable the computation of the CRC of a message by XORing the partial or incremental CRCs of composite sub-messages corresponding to the sub-messages. In a first method, the contents of an m-bit memory location are field squared and stepped to the next state as determined by the Galois field generated by the CRC generating polynomial to adjust the m-bit CRC. In a second method, the partial m-bit CRC of a sub-message is calculated according to CRC generating polynomial, P(x). A variable Y is calculated using a lookup table, where Y=xn modulo P(x). The partial m-bit CRC and Y are multiplied together and divided by P(x). The remainder of the division forms the adjusted m-bit CRC.

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of said first memory means for storing data, and a third memory for storing data connected to the output of said second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of the first memory means for storing data, and a third memory for storing data connected to the output of the second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

Abstract: A driver for an electro-optical transducer, such as a light-emitting diode (LED) is disclosed which shapes current pulses so as to contain "spikes" during turn-on and turn-off in order to quickly charge and discharge the junction and stray capacitances of the LED. Degeneration resistors interconnect the emitters of switching transistors used in a differential amplifier supplying the current to the LED and in a differential amplifier supplying a "peaking" current to the switching amplifier. A capacitor couples the amplifiers to conduct the additional current to the LED when it is initially turned on and charges the cathode of the LED. The emitter degeneration resistors couple the amplifiers to current sources and allow the amplifiers to be driven by emitter-coupled logic (ECL) gates without ringing. The resistors also linearize the transfer functions of the amplifiers so that the voltage swing of the ECL driver does not overly turn-off the transistors within the amplifiers, thereby improving response time.