Patents by Inventor Vichanart Nimibutr

Vichanart Nimibutr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127660
    Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Patent number: 11101200
    Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 24, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Publication number: 20200211936
    Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 2, 2020
    Applicant: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Publication number: 20200211935
    Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 2, 2020
    Applicant: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Patent number: 10211131
    Abstract: An integrated circuit device having improved delamination properties is provided. The integrated circuit may include a leadframe having a die support area supporting an integrated circuit die, and a plurality of leadframe leads. Surfaces of the leadframe leads are roughened by a roughening process to form roughened surfaces having an average roughness Ra. A thin plating layer is formed over the roughened leadframe lead surfaces, with a plating layer thickness of less than 40 times the roughness Ra of the leadframe lead surfaces, such that the thin plating layer is received into the roughened leadframe lead surface contours and thereby itself has a contoured outer surface. A molding material applied to the structure may directly contact and adhere to the contoured surface of the thin plating layer. The adhesion between the molding material and the contoured plating layer may reduce or eliminate delamination of the molding material from the leadframe.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: February 19, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Rangsun Kitnarong, Chawalit Pinyo, Vichanart Nimibutr, Vorawat Pangwong, Kritsada Inchum