Patents by Inventor Victor A. Holen

Victor A. Holen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Encryption of configuration stream
    Patent number: 6212639
    Abstract: A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 3, 2001
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Danesh Tavana, Victor A. Holen
  • FPGA architecture with repeatable titles including routing matrices and logic matrices
    Patent number: 5883525
    Abstract: An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: March 16, 1999
    Assignee: Xilinx, Inc.
    Inventors: Danesh Tavana, Wilson K. Yee, Victor A. Holen
  • FPGA architecture with repeatable tiles including routing matrices and logic matrices
    Patent number: 5682107
    Abstract: An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: October 28, 1997
    Assignee: Xilinx, Inc.
    Inventors: Danesh Tavana, Wilson K. Yee, Victor A. Holen