Abstract: A method of metalizing a ceramic member (e.g., lid or thermal base) for a semiconductor power device with a film of aluminum in an ion vapor deposition chamber in which an argon ion cloud is formed around the member within the chamber by biasing the member with a voltage and in which a continuous source of aluminum vapor is provided within the chamber so that aluminum ions are available to be accelerated towards the member from plural directions by the bias voltage, the aluminum ions being formed from the aluminum vapor upon passage through the argon ion cloud. The member may be an array of plates that are metalized before being separated. The metalized plates may be used as lids for semiconductor device packages or as thermal bases for power modules.

Abstract: A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.

Abstract: A power pack including a power device and driver circuit sandwiched between a base plate and a lid. The base plate and lid having flat exterior surfaces for bonding with heat exchangers and/or an external bus to provide both two-sided cooling and two-sided electrical access. The driver circuit and power device are spaced apart to allow parallel and separate thermal conduction paths to both the base plate and lid. The power pack further including a seal enclosing the power device and driver circuit between the base plate and lid.

Abstract: A circuit and method of protecting the antiparallel diodes of a power bridge circuit from stress induced failures caused by the fast operation of the power switches. An auxiliary power switch is provided in parallel to the main power switch which is operable during the reverse recovery of the antiparallel diode, after which the main power switch carries the bulk of the switch current.

Abstract: An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.

Abstract: A monolithic semiconductor power switching device and a method of separating plural thyristor based active areas therein includes reverse conducting diode regions between the active areas. The reverse conducting diode regions influence current flow at the edges of the operable ones of the active areas so that current from an operable one of the active areas does not flow into and turn on an inoperable one of the active areas. The reverse conducting diode regions have a width so that substantially all of the carriers of the current from an operable one of the active areas recombine before reaching an adjacent active area.

Abstract: A semiconductor device includes a semiconductor substrate forming the bottom portion of a package of the device and a ceramic plate forming the upper or lid portion of the device. The substrate includes a layer of metal on its upper surface along the substrate outer edge and spaced apart from electrodes on the substrate upper surface. The ceramic plate includes a copper foil on its lower surface along the outer edge thereof which overlaps and is bonded to the substrate metal layer. The ceramic plate has apertures therethrough which are sealed by copper foils on the inside of the package, the foils being bonded to respective ones of the substrate electrodes. A method of assembly comprises forming an array of integrally connected lids and an army of integrally connected substrates, each of the arrays including the aforementioned layers and foils, bonding the arrays together to form an array of devices, and dicing the bonded together arrays to provide individual devices.

Abstract: A compact package and a method of hermetically packaging a high power semiconductor device includes a metal lid bonded to a ceramic base with the semiconductor device therebetween. The lid is bonded to one surface of the device, and electrical contacts on the opposing surface of he device are bonded to foils that seal openings in the base for contact pins.

Abstract: An active clamp circuit for controlling over-voltage, surge conditions in electrical circuits. The active clamp includes a varistor which is switched into a circuit by a high power switch upon the detection of a surge condition. The use of a MOS Controlled Thyristor ("MCT") as a means for the switching the varistor permits the circuit to withstand a high di/dt and surge current while maintaining both on and off gated control of the switch.

Abstract: A semiconductor device includes a semiconductor substrate forming the bottom portion of a package of the device and a ceramic plate forming the upper or lid portion of the device. The substrate includes a layer of metal on its upper surface along the substrate outer edge and spaced apart from electrodes on the substrate upper surface. The ceramic plate includes a copper foil on its lower surface along the outer edge thereof which overlaps and is bonded to the substrate metal layer. The ceramic plate has apertures therethrough which are sealed by copper foils on the inside of the package, the foils being bonded to respective ones of the substrate electrodes.

Abstract: A package for one or more semiconductor devices has an electrically insulative and thermally conductive base on a thermally conductive support. The semiconductor devices may be enclosed in an encapsulant and are electrically contacted through leads that extend through the encapsulant.

Abstract: A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip, includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the name material am the power electrode.

Abstract: A package for semiconductor devices with plural subelements and method of packaging. Semiconductor power devices may include plural subelements to increase device manufacturing yield. Each subelement is separately contacted through the lid of the package by attaching a foil to a subelement contact and depending a tab from the foil that extends through the lid. Tabs for operative subelements can be connected external to the package, and tabs for inoperative subelements may be left unconnected or covered so that electrical connections cannot be made therewith.

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: A fast turn-on electrical switch circuit includes a silicon controlled rectifier ("SCR") connected substantially in parallel with a MOS controlled thyristor ("MCT"). When the switch is turned on, the MCT turns on almost immediately and carries the circuit load during the spreading time of the SCR. The SCR subsequently carries the circuit load when it is turned fully on because it has a smaller forward drop, due in part to its larger area and/or higher carrier lifetime. The MCT and SCR may be gated simultaneously from the same or separate sources or the SCR may be gated with a portion of the current from the MCT. The switch may be integrated into a single semiconductor device with alternating MCT regions and SCR regions.

Abstract: A compact package and a method of hermetically packaging a high power semiconductor device includes a metal lid bonded to a ceramic base with the semiconductor device therebetween. The lid is bonded to one surface of the device, and electrical contacts on the opposing surface of the device are bonded to foils that seal openings in the base for contact pins.

Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current). The invention finds application in both epitaxial grown and substrate based devices.

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the same material as the power electrode. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as active area of the chip.

Abstract: A four-region semiconductor device (that is a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.