Abstract: Active and standby clock signals are phase synchronized to each other within a predetermined phase tolerance by synchronizing each clock signal to the same reference pulse stream. A first synchronizing pulse signal is derived from the active clock signal and a second synchronizing pulse signal is derived from the standby clock signal. For each synchronizing pulse signal, the pulse widths exceed the reference signal pulse widths by an amount related to the predetermined phase tolerance. Synchronization between the active and standby clock signals is achieved when the phases of the active and standby clock signals are adjusted such that the pulse widths of the reference pulses lie entirely within the time domain of the pulse widths of the synchronizing pulse signals.