Patents by Inventor Victor Cher'Khng
Victor Cher'Khng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8373277Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: January 28, 2008Date of Patent: February 12, 2013Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7799610Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided.Type: GrantFiled: October 15, 2007Date of Patent: September 21, 2010Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7575953Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: December 18, 2007Date of Patent: August 18, 2009Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Publication number: 20080136045Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: ApplicationFiled: January 28, 2008Publication date: June 12, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7371608Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: March 14, 2003Date of Patent: May 13, 2008Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7358117Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: August 29, 2006Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7344969Abstract: Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.Type: GrantFiled: April 28, 2003Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7332819Abstract: Semiconductor devices and stacked die assemblies, are provided which have at least two semiconductor dies disposed on a substrate in a stacked arrangement, the first and second dies having first surfaces having bond pads, the second die having a second surface with a recessed edge portion along a perimeter of that die, and the recessed edge portion having a height sufficient for clearance of bonding elements extending from the first die.Type: GrantFiled: February 5, 2002Date of Patent: February 19, 2008Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7332820Abstract: Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.Type: GrantFiled: April 28, 2003Date of Patent: February 19, 2008Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7309623Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: August 29, 2006Date of Patent: December 18, 2007Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7282392Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: GrantFiled: August 29, 2006Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7282390Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided. In an embodiment of the methods, a second die is mounted on a first die which is at least partially received within a recess of the second die and an overall height of the dies within the device is less than a combined height of the dies.Type: GrantFiled: May 25, 2006Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour
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Patent number: 7112048Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: April 8, 2003Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20060006534Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.Type: ApplicationFiled: July 21, 2005Publication date: January 12, 2006Inventors: Tay Yean, Victor Cher Khng
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Publication number: 20050173788Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.Type: ApplicationFiled: April 8, 2005Publication date: August 11, 2005Inventors: Victor Cher'Khng, Lee Chai
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Patent number: 6720666Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: April 8, 2003Date of Patent: April 13, 2004Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Patent number: 6692987Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: GrantFiled: February 5, 2002Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20030211660Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: ApplicationFiled: April 8, 2003Publication date: November 13, 2003Applicant: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20030211659Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.Type: ApplicationFiled: April 8, 2003Publication date: November 13, 2003Applicant: Micron Technology, Inc.Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
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Publication number: 20030207515Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.Type: ApplicationFiled: April 28, 2003Publication date: November 6, 2003Applicant: Micron Technology, Inc., Boise, IDInventors: Hock Chuan Tan, Thiam Chye Lim, Victor Cher Khng Tan, Chee Peng Neo, Michael Kian Shing Tan, Beng Chye Chew, Cheng Poh Pour